公开(公告)号：US20220310363A1

公开(公告)日：2022-09-29

申请号：US17838855

申请日：2022-06-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Halbert CHONG ,  Rong TAO ,  Jianxin LEI ,  Rongjun WANG ,  Keith A. Miller ,  Irena H. Wysok ,  Tza-Jing Gung ,  Xing Chen

IPC: H01J37/32 ,  H01J37/34 ,  B08B5/00 ,  C23C14/50 ,  C23C14/34

Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.

公开(公告)号：US20210319989A1

公开(公告)日：2021-10-14

申请号：US16846502

申请日：2020-04-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Halbert CHONG ,  Rong TAO ,  Jianxin LEI ,  Rongjun WANG ,  Keith A. Miller ,  Irena H. Wysok ,  Tza-Jing Gung ,  Xing Chen

IPC: H01J37/32 ,  H01J37/34 ,  B08B5/00 ,  C23C14/50 ,  C23C14/34

Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.

公开(公告)号：US20140374907A1

公开(公告)日：2014-12-25

申请号：US14305906

申请日：2014-06-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Jick M. YU ,  Rong TAO

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. Modification of an upper portion of a metal seed layer allows for filling of the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free.

Abstract translation: 描述了一种装置和方法，其允许电镀在特征的侧壁的至少上部上使用非铜/预电镀层填充亚微米，高纵横比的半导体衬底特征，由此提供可靠的自下而上的积累 电镀填充材料的特点。 该设备和工艺消除了特征填充材料的空隙，并增强了与22,15,11和8nm的未来技术节点相关联的特征尺寸减小的电镀的可靠性。 金属种子层的上部的修改允许使用从特征的底部累积的电镀填充材料到可靠性和可预测性以及基本上无空隙来填充特征。

公开(公告)号：US20220310364A1

公开(公告)日：2022-09-29

申请号：US17838860

申请日：2022-06-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Halbert CHONG ,  Rong TAO ,  Jianxin LEI ,  Rongjun WANG ,  Keith A. Miller ,  Irena H. Wysok ,  Tza-Jing Gung ,  Xing Chen

IPC: H01J37/32 ,  H01J37/34 ,  B08B5/00 ,  C23C14/50 ,  C23C14/34

Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.

公开(公告)号：US20140305802A1

公开(公告)日：2014-10-16

申请号：US14205260

申请日：2014-03-11

Applicant: Applied Materials, Inc.

Inventor： Peijun DING ,  Rong TAO ,  Zheng XU ,  Daniel C. LUBBEN ,  Suraj RENGARAJAN ,  Michael A. MILLER ,  Arvind SUNDARRAJAN ,  Xianmin TANG ,  John C. FORSTER ,  Jianming FU ,  Roderick C. MOSELY ,  Fusen CHEN ,  Praburam GOPALRAJA

IPC: C23C14/04 ,  C23C14/35

CPC classification number: C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

Abstract translation: 用于溅射诸如钽，氮化钽和铜的沉积材料的磁控溅射反应器及其使用方法，其中促进了自离子等离子体（SIP）溅射和电感耦合等离子体（ICP）溅射，其一起或者 交替地，在相同或不同的室中。 此外，底部覆盖可以通过在一个室中的ICP再溅射和另一个室中的SIP来减薄或消除。 SIP由在溅射期间施加到靶的不均匀磁强度和高功率的磁极的小磁控管促进。 ICP由一个或多个将RF能量感应耦合到等离子体中的RF线圈提供。 组合的SIP-ICP层可以作为孔的衬垫或屏障或种子或成核层。 此外，可以在ICP溅射期间溅射RF线圈以提供保护材料。 在另一个腔室中，辅助磁体阵列沿磁控溅射反应器的侧壁朝着晶片从目标侧面定位。 磁控管优选地是小而强的，具有围绕第二磁极性较弱的外极的第一磁极的更强的外极并围绕腔的中心轴旋转。 辅助磁体优选地具有第一磁极以将不平衡的磁场分量拉向晶片。 辅助磁体可以是永磁体或电磁体。

公开(公告)号：US20180327893A1

公开(公告)日：2018-11-15

申请号：US16033166

申请日：2018-07-11

Applicant: Applied Materials, Inc.

Inventor： Peijun DING ,  Rong TAO ,  Zheng XU ,  Daniel C. LUBBEN ,  Suraj RENGARAJAN ,  Michael A. MILLER ,  Arvind SUNDARRAJAN ,  Xianmin TANG ,  John C. FORSTER ,  Jianming FU ,  Roderick C. MOSELY ,  Fusen CHEN ,  Praburam GOPALRAJA

IPC: C23C14/04 ,  C23C14/56 ,  C23C14/35 ,  H01J37/32 ,  H01J37/34 ,  H01L21/285 ,  H01L21/768 ,  C23C14/34

CPC classification number: C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

公开(公告)号：US20150136732A1

公开(公告)日：2015-05-21

申请号：US14547702

申请日：2014-11-19

Applicant: Applied Materials, Inc.

Inventor： Xianmin TANG ,  Ludovic GODET ,  Guojun LIU ,  Jing TANG ,  Phillip STOUT ,  Rong TAO

IPC: C23C16/56 ,  C23C14/50 ,  C23C16/458 ,  C23C14/00

CPC classification number: C23C14/046

Abstract: A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices.

Abstract translation: 描述了一种在衬底上沉积膜的方法和装置。 该方法包括在其上或其上形成特征的基底上沉积膜。 该特征包括处于不同水平的第一表面和第二表面。 通过将衬底暴露于来自线性离子源的离子通量来去除沉积膜的至少一部分。 离子通量具有小于或等于90度且大于或等于15度的离子角度扩展。 在某些实施例中，特征可以是纳米尺度的高纵横比特征，例如窄的，深的沟槽，小直径，深孔或双镶嵌结构。 这些特征通常在集成电路器件中找到。