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    METHOD FOR STABILIZING AN INTERFACE POST ETCH TO MINIMIZE QUEUE TIME ISSUES BEFORE NEXT PROCESSING STEP
    1.
    发明申请
    METHOD FOR STABILIZING AN INTERFACE POST ETCH TO MINIMIZE QUEUE TIME ISSUES BEFORE NEXT PROCESSING STEP 审中-公开
    用于在接下来的处理步骤之前稳定接口后处理以最小化队列时间问题的方法

    公开(公告)号：US20150079799A1

    公开(公告)日：2015-03-19

    申请号：US14029771

    申请日：2013-09-17

    Applicant: Applied Materials, Inc.

    Inventor： Srinivas D. NEMANI ,  Praburam GOPALRAJA ,  Takehito KOSHIZAWA

    IPC: H01L21/3065

    CPC classification number: H01L21/31116 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063

    Abstract: Methods for etching a dielectric barrier layer disposed on the substrate using a low temperature etching process along with a subsequent interface protection layer deposition process are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes transferring a substrate having a dielectric barrier layer disposed thereon into an etching processing chamber, performing a treatment process on the dielectric barrier layer, remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the treated dielectric barrier layer disposed on the substrate, plasma annealing the dielectric barrier layer to remove the dielectric barrier layer from the substrate, and forming an interface protection layer after the dielectric barrier is removed from the substrate.

    Abstract translation: 提供了使用低温蚀刻工艺以及随后的界面保护层沉积工艺来蚀刻设置在基板上的电介质阻挡层的方法。 在一个实施例中，用于蚀刻设置在基板上的电介质阻挡层的方法包括将其上设置有介电阻挡层的基板转印到蚀刻处理室中，对介电阻挡层进行处理工艺，在蚀刻中远程产生等离子体 气体混合物供应到蚀刻处理室中以蚀刻设置在基板上的经处理的介电阻挡层，等离子体对介电阻挡层进行退火以从基板移除电介质阻挡层，并且在介电阻挡层从基板去除之后形成界面保护层 基质。

    SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOMETER TECHNOLOGY
    3.
    发明申请
    SELF-ALIGNED MULTIPLE SPACER PATTERNING SCHEMES FOR ADVANCED NANOMETER TECHNOLOGY 有权
    高分辨率纳米技术的自对准多层间距图案

    公开(公告)号：US20150371852A1

    公开(公告)日：2015-12-24

    申请号：US14730194

    申请日：2015-06-03

    Applicant: Applied Materials, Inc.

    Inventor： Ying ZHANG ,  Uday MITRA ,  Praburam GOPALRAJA ,  Srinivas D. NEMANI ,  Hua CHUNG

    IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

    CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

    Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

    Abstract translation: 本公开提供形成具有尺寸在14纳米以下的特征的精确尺寸控制和最小光刻相关误差的纳米结构。 本文提供了自对准多间隔图案（SAMSP）工艺，并且该工艺利用最小光刻曝光工艺，而是采用多次沉积/蚀刻工艺来逐渐减小沿制造工艺在掩模中形成的特征尺寸，直到期望的极小尺寸 在掩模层中形成纳米结构。

    ADDITIVE PATTERNING OF SEMICONDUCTOR FILM STACKS
    4.
    发明申请
    ADDITIVE PATTERNING OF SEMICONDUCTOR FILM STACKS 有权

    公开(公告)号：US20210305501A1

    公开(公告)日：2021-09-30

    申请号：US17328491

    申请日：2021-05-24

    Applicant: Applied Materials, Inc.

    Inventor： John O. DUKOVIC ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Praburam GOPALRAJA ,  Steven Hiloong WELCH ,  Bhargav S. CITLA

    IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

    SPUTTERING SHOWERHEAD
    6.
    发明申请
    SPUTTERING SHOWERHEAD 审中-公开

    公开(公告)号：US20180087155A1

    公开(公告)日：2018-03-29

    申请号：US15704850

    申请日：2017-09-14

    Applicant: Applied Materials, Inc.

    Inventor： Anantha K. SUBRAMANI ,  Tza-Jing GUNG ,  Praburam GOPALRAJA ,  Hari K. PONNEKANTI

    IPC: C23C16/455 ,  C23C14/34 ,  C23C14/35 ,  H01J37/34 ,  C23C28/02 ,  C23C28/04

    Abstract: In one implementation, a sputtering showerhead assembly is provided. The sputtering showerhead assembly comprises a faceplate comprising a sputtering surface comprising a target material and a second surface opposing the sputtering surface, wherein a plurality of gas passages extend from the sputtering surface to the second surface. The sputtering showerhead assembly comprises further comprises a backing plate positioned adjacent to the second surface of the faceplate. The backing plate comprises a first surface and a second surface opposing the first surface. The sputtering showerhead assembly has a plenum defined by the first surface of the backing plate and the second surface of the faceplate. The sputtering showerhead assembly comprises further comprises one or more magnetrons positioned along the second surface of the backing plate.

    ADDITIVE PATTERNING OF SEMICONDUCTOR FILM STACKS
    8.
    发明申请
    ADDITIVE PATTERNING OF SEMICONDUCTOR FILM STACKS 有权

    公开(公告)号：US20210035619A1

    公开(公告)日：2021-02-04

    申请号：US16525470

    申请日：2019-07-29

    Applicant: Applied Materials, Inc.

    Inventor： John O. DUKOVIC ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Praburam GOPALRAJA ,  Steven Hiloong WELCH ,  Bhargav S. CITLA

    IPC: G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

    SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING
    9.
    发明申请
    SELF-IONIZED AND INDUCTIVELY-COUPLED PLASMA FOR SPUTTERING AND RESPUTTERING 审中-公开
    自放电和感应耦合等离子喷溅和调光

    公开(公告)号：US20140305802A1

    公开(公告)日：2014-10-16

    申请号：US14205260

    申请日：2014-03-11

    Applicant: Applied Materials, Inc.

    Inventor： Peijun DING ,  Rong TAO ,  Zheng XU ,  Daniel C. LUBBEN ,  Suraj RENGARAJAN ,  Michael A. MILLER ,  Arvind SUNDARRAJAN ,  Xianmin TANG ,  John C. FORSTER ,  Jianming FU ,  Roderick C. MOSELY ,  Fusen CHEN ,  Praburam GOPALRAJA

    IPC: C23C14/04 ,  C23C14/35

    CPC classification number: C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/35 ,  C23C14/358 ,  C23C14/564 ,  C23C14/568 ,  H01J37/321 ,  H01J37/3402 ,  H01J37/3408 ,  H01J37/3441 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

    Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target. The magnetron preferably is a small, strong one having a stronger outer pole of a first magnetic polarity surrounding a weaker outer pole of a second magnetic polarity and rotates about the central axis of the chamber. The auxiliary magnets preferably have the first magnetic polarity to draw the unbalanced magnetic field component toward the wafer. The auxiliary magnets may be either permanent magnets or electromagnets.

    Abstract translation: 用于溅射诸如钽，氮化钽和铜的沉积材料的磁控溅射反应器及其使用方法，其中促进了自离子等离子体（SIP）溅射和电感耦合等离子体（ICP）溅射，其一起或者 交替地，在相同或不同的室中。 此外，底部覆盖可以通过在一个室中的ICP再溅射和另一个室中的SIP来减薄或消除。 SIP由在溅射期间施加到靶的不均匀磁强度和高功率的磁极的小磁控管促进。 ICP由一个或多个将RF能量感应耦合到等离子体中的RF线圈提供。 组合的SIP-ICP层可以作为孔的衬垫或屏障或种子或成核层。 此外，可以在ICP溅射期间溅射RF线圈以提供保护材料。 在另一个腔室中，辅助磁体阵列沿磁控溅射反应器的侧壁朝着晶片从目标侧面定位。 磁控管优选地是小而强的，具有围绕第二磁极性较弱的外极的第一磁极的更强的外极并围绕腔的中心轴旋转。 辅助磁体优选地具有第一磁极以将不平衡的磁场分量拉向晶片。 辅助磁体可以是永磁体或电磁体。

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