公开(公告)号：US20150262828A1

公开(公告)日：2015-09-17

申请号：US14627861

申请日：2015-02-20

Applicant: APPLIED MATERIALS, INC.

Inventor： ADAM BRAND ,  NAOMI YOSHIDA ,  SESHADRI GANGULI ,  DAVID THOMPSON ,  MEI CHANG

IPC: H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/3065

CPC classification number: H01L21/823842 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/78696

Abstract: Methods for forming a multi-threshold voltage device on a substrate are provided herein. In some embodiments, the method of forming a multi-threshold voltage device may include (a) providing a substrate having a first layer disposed thereon, wherein the substrate comprises a first feature and a second feature disposed within the first layer; (b) depositing a blocking layer atop the substrate; (c) selectively removing a portion of the blocking layer from atop the substrate to expose the first feature; (d) selectively depositing a first work function layer atop the first feature; (e) removing a remainder of the blocking layer to expose the second feature; and (f) depositing a second work function layer atop the atop the first work function layer and the second feature.

Abstract translation: 本文提供了在基板上形成多阈值电压装置的方法。 在一些实施例中，形成多阈值电压装置的方法可以包括（a）提供其上设置有第一层的衬底，其中衬底包括设置在第一层内的第一特征和第二特征; （b）在衬底顶上沉积阻挡层; （c）从所述衬底顶部选择性地去除所述阻挡层的一部分以暴露所述第一特征; （d）在所述第一特征顶部选择性地沉积第一功函数层; （e）去除所述阻挡层的剩余部分以暴露所述第二特征; 以及（f）在第一功能层和第二特征顶部之上沉积第二功函数层。

公开(公告)号：US20210320064A1

公开(公告)日：2021-10-14

申请号：US17356717

申请日：2021-06-24

Applicant: APPLIED MATERIALS, INC.

Inventor： SUKETU A. PARIKH ,  RONG TAO ,  ROEY SHAVIV ,  JOUNG JOO LEE ,  SESHADRI GANGULI ,  SHIRISH PETHE ,  DAVID GAGE ,  JIANSHE TANG ,  MICHAEL A STOLFI

IPC: H01L23/528 ,  H01L21/67 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

公开(公告)号：US20140273515A1

公开(公告)日：2014-09-18

申请号：US14211156

申请日：2014-03-14

Applicant: Applied Materials, Inc.

Inventor： AVGERINOS V. GELATOS ,  SRINIVAS GANDIKOTA ,  SESHADRI GANGULI ,  XINYU FU ,  BO ZHENG ,  YU LEI

IPC: H01L21/67 ,  H01L21/285

CPC classification number: H01L21/6723 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/285 ,  H01L21/28525 ,  H01L21/28568 ,  H01L21/6719 ,  H01L21/67207 ,  H01L29/4958 ,  H01L29/4966

Abstract: Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).

Abstract translation: 本文提供了用于制造n型金属氧化物半导体（NMOS）器件的集成平台的实施例。 在一些实施例中，用于制造n型金属氧化物半导体（NMOS）器件的集成平台可以包括第一沉积室，其被配置为在衬底顶部沉积第一层，第一层包含氧化钛（TiO 2）或硒（Se）; 第二沉积室，被配置为在所述第一层顶部沉积第二层，所述第二层包含钛; 第三沉积室，被配置为在所述第二层顶部沉积第三层，所述第三层包括氮化钛（TiN）或氮化钨（WN）之一。

公开(公告)号：US20210020569A1

公开(公告)日：2021-01-21

申请号：US16516817

申请日：2019-07-19

Applicant: APPLIED MATERIALS, INC.

Inventor： SUKETU A. PARIKH ,  RONG TAO ,  ROEY SHAVIV ,  JOUNG JOO LEE ,  SESHADRI GANGULI ,  SHIRISH PETHE ,  DAVID GAGE ,  JIANSHE TANG ,  MICHAEL A. STOLFI

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/67

Abstract: Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1× feature and at least one wider than 1× feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1× feature and at least one wider than 1× feature; the first metal material is reflowed such that the at least one 1× feature is filled with the first metal material and the at least one wider than 1× feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1× feature is filled with the second metal material.

公开(公告)号：US20200343136A1

公开(公告)日：2020-10-29

申请号：US16396744

申请日：2019-04-28

Applicant: APPLIED MATERIALS, INC.

Inventor： SANG-HO YU ,  SESHADRI GANGULI

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/285

Abstract: Methods and apparatus for filling a high aspect ratio feature such as a via with ruthenium including: contacting a ruthenium liner with a ruthenium precursor within a high aspect ratio feature such as a via, wherein the ruthenium liner has a top surface within a high aspect ratio feature such as a via, and wherein the top surface comprises a halogen material such as iodine or bromine. Embodiments also relate to selective deposition of ruthenium within a high-aspect ratio feature such as a via.