公开(公告)号：US20180090323A1

公开(公告)日：2018-03-29

申请号：US15566694

申请日：2016-04-12

Applicant: EUGENE TECHNOLOGY CO., LTD.

Inventor： Woo Duck JUNG ,  Sung Tae JE ,  Kyu Jin CHOI ,  Seong Min HAN

IPC: H01L21/205 ,  H01L21/02 ,  H01L21/683

CPC classification number: H01L21/2053 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/205 ,  H01L21/67109 ,  H01L21/67303 ,  H01L21/683

Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes a tube having an inner space, a substrate support on which a plurality of substrates are stacked in multistage within the tube, the substrate support individually defining a plurality of processing spaces in which the plurality of substrates are respectively processed, a first gas supply part configured to supply a first gas into all the plurality of processing spaces, a second gas supply part comprising a plurality of injectors disposed to respectively correspond to the plurality of processing spaces so that the second gas is individually supplied onto each of the plurality of substrates, and an exhaust part configured to exhaust the gases within the tube. Thus, the gas may be individually supplied into each of the processing spaces in which the plurality of substrates are respectively processed.

公开(公告)号：US20170263602A1

公开(公告)日：2017-09-14

申请号：US15592256

申请日：2017-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsin HU ,  Hsueh-Shih Fan ,  Huan-Tsung Huang

IPC: H01L27/06 ,  H01L29/16 ,  H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/2053 ,  H01L21/76895 ,  H01L21/823431 ,  H01L23/535 ,  H01L28/20 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66166 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.

公开(公告)号：US20160223749A1

公开(公告)日：2016-08-04

申请号：US14987710

申请日：2016-01-04

Applicant: The Research Foundation for the State University of New York

Inventor： Douglas Coolbaugh ,  Thomas Adam ,  Gerald L. Leake

IPC: G02B6/13 ,  G02B6/134 ,  G02B6/136 ,  G02B6/12 ,  H01L31/0232 ,  G02B6/132

CPC classification number: G02B6/13 ,  G02B6/12002 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B6/43 ,  G02B2006/121 ,  G02B2006/12104 ,  G02B2006/12123 ,  G02B2006/12169 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2033 ,  H01L21/2053 ,  H01L27/14625 ,  H01L27/14629 ,  H01L31/022408 ,  H01L31/0232 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1808 ,  Y02E10/52 ,  Y02E10/547

Abstract: A photonic structure can include in one aspect one or more waveguides formed by patterning of waveguiding material adapted to propagate light energy. Such waveguiding material may include one or more of silicon (single-, poly-, or non-crystalline) and silicon nitride.

Abstract translation: 光子结构可以在一个方面包括通过对适于传播光能的波导材料的图案化形成的一个或多个波导。 这种波导材料可以包括硅（单晶，多晶或非晶）和氮化硅中的一种或多种。

公开(公告)号：US20180226352A1

公开(公告)日：2018-08-09

申请号：US15809261

申请日：2017-11-10

Applicant: International Business Machines Corporation

Inventor： Praneet ADUSUMILLI ,  Hemanth JAGANNATHAN ,  Christian LAVOIE ,  Jean L. SWEET

IPC: H01L23/532 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/324 ,  H01L21/205 ,  H01L21/8234

CPC classification number: H01L23/53209 ,  H01L21/2053 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53266 ,  H01L27/092

Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a bottom film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured bottom silicide film layer directly on the epitaxially grown source-drain contact region. A top metal film layer is deposited on the textured bottom silicide film layer. A second anneal forms a textured top metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.

公开(公告)号：US09299702B2

公开(公告)日：2016-03-29

申请号：US14229102

申请日：2014-03-28

Applicant: Samar Saha

Inventor： Samar Saha

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/0262 ,  H01L21/2053 ,  H01L21/2257 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/105 ,  H01L29/1083

Abstract: A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors.

Abstract translation: 一种晶体管结构，其具有沉积在植入的衬底上的外延层，以便减少工艺变异性。 外延层能够通过从注入衬底的上扩散沉积掺杂，未掺杂或轻掺杂，并用于形成晶体管结构的沟道。 因此，尽管晶体管的物理尺寸较小，但是这种使用未掺杂的外延层提供了降低工艺变化性（例如随机掺杂剂波动）以及因此晶体管性能可变性的优点。

公开(公告)号：US09263263B2

公开(公告)日：2016-02-16

申请号：US13944592

申请日：2013-07-17

Applicant: IMEC

Inventor： Andriy Hikavyy ,  Benjamin Vincent ,  Roger Loo

IPC: H01L21/02 ,  H01L21/205

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2053

Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Abstract translation: 公开了用于选择性沉积掺杂的IV-Sn族材料的方法。 在一些实施例中，该方法包括提供包括至少第一区域和第二区域的图案化衬底，其中第一区域包括暴露的第一半导体材料，并且第二区域包括暴露的绝缘体材料，并且执行至少两个循环 生长蚀刻循环过程。 每个循环包括沉积掺杂的IV族锡（Sn）层，其中沉积掺杂的IV-Sn层包括提供IV族前体，Sn前体和掺杂剂前体，并使用蚀刻气体来回蚀刻沉积 掺杂IV-Sn层。

公开(公告)号：US20150214117A1

公开(公告)日：2015-07-30

申请号：US14678024

申请日：2015-04-03

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  ALI KHAKIFIROOZ ,  ALEXANDER REZNICEK ,  GHAVAM G. SHAHIDI

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/033 ,  H01L21/2018 ,  H01L21/2053 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

公开(公告)号：US20140264325A1

公开(公告)日：2014-09-18

申请号：US14204535

申请日：2014-03-11

Applicant: U.S.A. as represented by the Administrator of the National Aeronautics and Space Administration

Inventor： Yeonjoon Park ,  Sang Hyouk Choi

IPC: H01L29/04 ,  H01L21/02 ,  H01L29/20 ,  H01L29/22

CPC classification number: H01L21/0242 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/2011 ,  H01L21/2053 ,  H01L21/2056 ,  H01L25/167 ,  H01L27/15 ,  H01L29/267 ,  H01L31/028 ,  H01L31/0336 ,  H01L31/03682 ,  H01L31/125 ,  H01L31/1804 ,  H01L31/1812 ,  H01L31/1848 ,  H01L31/1852 ,  H01L33/007 ,  H01L2924/0002 ,  Y02E10/544 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  H01L2924/00

Abstract: One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Abstract translation: 本发明的一个方面是一种双面混合晶体结构，其包括具有（0001）C面并具有正面和背面的三角形蓝宝石晶片。 蓝宝石晶片对可见光和红外光谱的光线基本上是透明的，并且还提供了关于电磁射频噪声的绝缘。 在（0001）C面上具有与立方晶体方向对准的立方菱形结构的晶体Si材料层，并应变为菱面体，从而使选定的（SiGe）器件能够连续地集成到蓝宝石的后侧 晶圆。 双面混合晶体结构还包括在蓝宝石晶片的正面上的集成III-氮化物晶体层，其能够在蓝宝石晶片的正面上连续地集成所选择的III-氮化物器件。

公开(公告)号：US20130175546A1

公开(公告)日：2013-07-11

申请号：US13734986

申请日：2013-01-06

Applicant: Adam Khan

Inventor： Adam Khan

IPC: H01L21/205 ,  H01L29/16

CPC classification number: H01L21/0415 ,  H01L21/02085 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02444 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/043 ,  H01L21/2053 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/1602 ,  H01L29/1606 ,  H01L29/6603 ,  H01L29/66045 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/868 ,  H01L31/028 ,  H01L33/005 ,  H01L33/34 ,  Y02E10/547

Abstract: Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein at least 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K.

Abstract translation: 本文公开了一种用于制造单片集成金刚石半导体的新的和改进的系统和方法。 该方法可以包括以下步骤：将衬底材料的表面接合，在衬底材料的表面上形成金刚石层; 以及在所述金刚石层内形成半导体层，其中所述半导体层的所述金刚石半导体具有n型施主原子和金刚石晶格，其中至少0.16％的所述施主原子贡献具有大于770cm 2 / Vs的迁移率的传导电子， 金刚石晶格在100 kPa和300K。

公开(公告)号：US11708646B2

公开(公告)日：2023-07-25

申请号：US17562438

申请日：2021-12-27

Applicant: SHOWA DENKO K.K.

Inventor： Rimpei Kindaichi

IPC: C30B23/02 ,  C30B35/00 ,  H01L21/205 ,  C30B23/06 ,  C30B29/36

CPC classification number: C30B35/002 ,  C30B23/025 ,  C30B23/066 ,  C30B29/36 ,  H01L21/2053

Abstract: A silicon carbide single crystal manufacturing apparatus includes a crucible constituted by a crucible body and a crucible lid and a base having a crucible lid side surface supported by the lower surface of the crucible lid, and a seed crystal mounting surface on which the seed crystal is mounted and which is a surface on the opposite side of the crucible lid side surface, wherein the base is made of graphite material, the area of the seed crystal mounting surface is larger than the area of the crucible lid side surface, and the base has at least of a portion in which the cross-sectional area orthogonal to the vertical direction connecting the crucible lid side surface and the seed crystal mounting surface is gradually reduced, and a portion that is getting smaller gradually, from the surface of the seed crystal mounting surface toward the crucible lid side surface.