公开(公告)号：US20180061978A1

公开(公告)日：2018-03-01

申请号：US15804691

申请日：2017-11-06

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Naomi YOSHIDA ,  Theresa Kramer GUARINI ,  Sung Won JUN ,  Vanessa PENA ,  Errol Antonio C. SANCHEZ ,  Benjamin COLOMBEAU ,  Michael CHUDZIK ,  Bingxi Sun WOOD ,  Nam Sung KIM

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20170309719A1

公开(公告)日：2017-10-26

申请号：US15494981

申请日：2017-04-24

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Nam Sung KIM ,  Bingxi Sun WOOD ,  Naomi YOSHIDA ,  Sheng-Chin KUNG ,  Miao JIN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

公开(公告)号：US20180122945A1

公开(公告)日：2018-05-03

申请号：US15490593

申请日：2017-04-18

Applicant: Applied Materials, Inc.

Inventor： Chih-Yang CHANG ,  Raymond Hoiman HUNG ,  Tatsuya E. SATO ,  Nam Sung KIM ,  Shiyu SUN ,  Bingxi Sun WOOD

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66795

Abstract: Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.

公开(公告)号：US20170194430A1

公开(公告)日：2017-07-06

申请号：US15395928

申请日：2016-12-30

Applicant: Applied Materials, Inc.

Inventor： Bingxi Sun WOOD ,  Michael G. WARD ,  Shiyu SUN ,  Michael CHUDZIK ,  Nam Sung KIM ,  Hua CHUNG ,  Yi-Chiau HUANG ,  Chentsau YING ,  Ying ZHANG ,  Chi-Nung NI ,  Lin DONG ,  Dongqing YANG

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/764 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.

公开(公告)号：US20220173220A1

公开(公告)日：2022-06-02

申请号：US17672788

申请日：2022-02-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu SUN ,  Nam Sung KIM ,  Bingxi Sun WOOD ,  Naomi YOSHIDA ,  Sheng-Chin KUNG ,  Miao JIN

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

公开(公告)号：US20150118832A1

公开(公告)日：2015-04-30

申请号：US14062638

申请日：2013-10-24

Applicant: Applied Materials, Inc.

Inventor： Bingxi Sun WOOD ,  Li Yan MIAO ,  Huixiong DAI ,  Adam BRAND ,  Yongmei CHEN ,  Mandar B. PANDIT ,  Qingjun ZHOU

IPC: H01L21/266 ,  H01L21/3105

CPC classification number: H01L21/266 ,  H01L21/26586 ,  H01L21/31053 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66803

Abstract: Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate.

Abstract translation: 本发明的实施例提供了一种用于对具有用于离子注入工艺的良好工艺控制的硬掩模层图案化的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）。 在一个实施例中，图案化设置在衬底上的硬掩模层的方法包括在设置在衬底上的硬掩模层上形成平坦化层，在平坦化层上设置图案化的光致抗蚀剂层，将平坦化层和硬掩模层图案化， 在处理室中的图案化光致抗蚀剂层，暴露下面的衬底的第一部分，以及从衬底去除平坦化层。