-
公开(公告)号：US06614283B1
公开(公告)日：2003-09-02
申请号：US10126564
申请日：2002-04-19
IPC分类号： H03L500
CPC分类号： H03K3/356113 , H03K17/102
摘要： In an integrated circuit, a voltage level shifter transitions an input signal at a first voltage level to an output signal at a second voltage level. The voltage level shifter generally includes switching elements, such as transistors, that control switching the output signal between logical zero and logical one values. The switching elements have a maximum voltage below which they can operate. The maximum voltage is less than the second voltage level. The voltage across the switching elements is limited to less than the maximum voltage.
摘要翻译： 在集成电路中，电压电平移位器将第一电压电平的输入信号转换为第二电压电平的输出信号。 电压电平移位器通常包括开关元件，例如晶体管，其控制逻辑零和逻辑一个值之间的输出信号的切换。 开关元件的最大电压低于它们可以工作的电压。 最大电压小于第二电压电平。 开关元件两端的电压被限制在小于最大电压。
-
公开(公告)号：US08310021B2
公开(公告)日：2012-11-13
申请号：US12835313
申请日：2010-07-13
IPC分类号： H01L31/115
CPC分类号： H01L31/1892 , G01T3/08 , H01L31/115 , Y02E10/50
摘要： A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.
摘要翻译： 制造中子检测器的方法包括：通过至少在衬底上形成氧化层来形成第一晶片，在氧化层上形成有源半导体层，以及在有源半导体层上形成互连层，形成至少一个导电 从所述互连层延伸穿过所述有源半导体层和所述氧化物层，在所述互连层和第二晶片之间形成电路转移键，在形成所述电路转移键之后移除所述第一晶片的所述衬底， 在去除第一晶片的衬底之后，其中所述接合焊盘电连接到所述导电通路，在去除所述第一晶片的衬底之后，在所述氧化物层上沉积阻挡层，以及在所述阻挡层上沉积中子转换层 沉积阻挡层后的层。
-
公开(公告)号：US20120228513A1
公开(公告)日：2012-09-13
申请号：US13424269
申请日：2012-03-19
IPC分类号： G01T1/24
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
-
公开(公告)号：US06924689B2
公开(公告)日：2005-08-02
申请号：US10166309
申请日：2002-06-10
申请人： Todd A. Randazzo , E. Wayne Porter
发明人： Todd A. Randazzo , E. Wayne Porter
CPC分类号： G05F3/242 , H03K3/356113 , H03K3/356147
摘要： A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.
摘要翻译： 用于输入使用参考电压源的输出电压电平移位器的核心电压以产生参考电压，以限制连接到电压敏感开关器件的至少一个电压敏感节点上的漏极电压，所述电压敏感节点位于高电压域 。 反馈线从电压敏感节点延伸到参考电压源。 反馈结构响应于至少一个电压敏感节点上的漏极电压而改变参考电压，从而将漏极电压维持在基本恒定的期望值。
-
公开(公告)号：US06825546B1
公开(公告)日：2004-11-30
申请号：US10035346
申请日：2001-12-28
申请人： John Q. Walker , Todd A. Randazzo
发明人： John Q. Walker , Todd A. Randazzo
IPC分类号： H01L2993
CPC分类号： H01L29/93
摘要： A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.
摘要翻译： 在耗尽区中形成具有逆向掺杂剂浓度分布的半导体结的变容二极管。 逆向掺杂剂浓度分布导致变容二极管的近似线性电容/电压特性响应。 逆向掺杂剂浓度分布还使得掺杂剂浓度的峰值能够用作连接到变容二极管的低电阻导电路径。
-
公开(公告)号：US06545305B1
公开(公告)日：2003-04-08
申请号：US09550381
申请日：2000-04-14
申请人： Todd A. Randazzo
发明人： Todd A. Randazzo
IPC分类号： H01L27108
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.
摘要翻译： 一个金属到多晶硅电容器的电容器。 通过在衬底上形成场氧化物层来制造电容器。 然后，在场氧化物层上形成多晶硅段。 该多晶硅段形成用于电容器的多晶硅底板。 形成介电层并进行平面化处理。 在电介质层中形成一个开口以暴露多晶硅段的一部分。 然后，在多晶硅段的暴露部分上形成氧化物层。 在开口上的氧化物层上形成金属段，其中金属段形成半导体器件的顶板。
-
公开(公告)号：US06501318B1
公开(公告)日：2002-12-31
申请号：US09848942
申请日：2001-05-04
IPC分类号： H03K508
CPC分类号： H03K19/00315 , H03K19/09432
摘要： A high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.
摘要翻译： 具有与正电压源电连通的第一连接和与负电压源电连通的第二连接的高速输入缓冲器。 第一原生晶体管功能地设置在正电压源和第一连接之间。 第一天然晶体管的第一接触电连接到正电压源，并且第一天然晶体管的第二接触电连接到第一连接。 第二本机晶体管功能地设置在负电压源和第二连接之间。 第二天体晶体管的第一接触电连接到负电压源，并且第二天体晶体管的第二接触电连接到第二连接。
-
8.发明授权Semiconductor device with a pair of transistors having dual work function gate electrodes 有权具有双工作功能栅电极的一对晶体管的半导体器件公开(公告)号：US06211555B1
公开(公告)日：2001-04-03
申请号：US09162407
申请日：1998-09-29
申请人： Todd A. Randazzo , Jan Kolnik
发明人： Todd A. Randazzo , Jan Kolnik
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/823443 , H01L21/82345 , H01L21/823493 , H01L29/42364 , H01L29/4983 , H01L29/7833 , H01L29/7836
摘要： Techniques are described for fabricating a pair of &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. In particular, the lengths of respective channel regions for the transistors are substantially the same, and portions of each gate electrode extending above a channel region include only dopants of a single conductivity type. The techniques can be incorporated into a standard CMOS process.
摘要翻译： 描述了用于制造一对β相同晶体管的技术，换句话说，一对晶体管，其尺寸和电特性（它们各自的栅电极功函数除外）基本相似。 特别地，用于晶体管的各个沟道区的长度基本上相同，并且在沟道区上方延伸的每个栅极的部分仅包括单一导电类型的掺杂剂。 这些技术可以并入标准的CMOS工艺。
-
公开(公告)号：US6090656A
公开(公告)日：2000-07-18
申请号：US74837
申请日：1998-05-08
申请人： Todd A. Randazzo
发明人： Todd A. Randazzo
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8242
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.
-
10.发明授权Simple BICMOS process for creation of low trigger voltage SCR and zener diode pad protection 失效用于创建低触发电压SCR和齐纳二极管焊盘保护的简单BICMOS工艺
公开(公告)号：US5821572A
公开(公告)日：1998-10-13
申请号：US768905
申请日：1996-12-17
IPC分类号： H01L27/02 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0262
摘要： The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.
摘要翻译： 本发明提供了具有第一类导电性的衬底中的半导体保护器件。 半导体保护器件包括两个垂直双极晶体管。 阱区位于衬底内，具有第二类导电性，阱区内具有第一类导电性。 具有第二类型导电性的第一掺杂区域和具有第一类型导电性的第二掺杂区域位于阱区域内。 具有第二类型导电性的第三掺杂区域和具有第一类型导电性的第四掺杂区域位于基极区域内。 具有第一类型导电性的掺杂区域位于衬底内。 该掺杂区域连接到第四掺杂区域。
-
-
-
-
-
-
-
-
-
搜索结果
46 条记录 (耗时 0.027 秒)
