公开(公告)号：US5643640A

公开(公告)日：1997-07-01

申请号：US563165

申请日：1995-11-27

申请人： Ashima B. Chakravarti ,  Terry M. Cheng ,  Son Van Nguyen ,  Michael Shapiro

发明人： Ashima B. Chakravarti ,  Terry M. Cheng ,  Son Van Nguyen ,  Michael Shapiro

IPC分类号： C03C3/112 ,  C23C16/40 ,  B05D3/06

CPC分类号： C03C3/112 ,  C23C16/401

摘要： A fluorinated phosphosilicate glass (FPSG) is produced in a plasma-enhanced chemical vapor deposition process (PECVD) in which the plasma source comprises conventional phosphosilicate glass-forming materials together with one or more fluorine gas-forming materials. The deposited fluorine-gas enhances the filling of gaps or voids with dielectric glass compositions by etching the top of the via holes or gaps during the filling operation. The present fluorine-doped phosphosilicate glass compositions are stable compared to conventional phosphosilicate glass compositions which are relatively unstable and unsatisfactory for use as gap-filling dielectric glass compositions.

摘要翻译： 在等离子体增强化学气相沉积工艺（PECVD）中生产氟化磷硅酸盐玻璃（FPSG），其中等离子体源包含常规的磷硅酸盐玻璃形成材料以及一种或多种氟气形成材料。 沉积的氟气通过在填充操作期间蚀刻通孔或间隙的顶部来增强用电介质玻璃组合物填充间隙或空隙。 本发明的氟掺杂磷硅酸盐玻璃组合物与常规的磷硅酸盐玻璃组合物相比是稳定的，这些组合物相对不稳定并且不能令人满意地用作间隙填充电介质玻璃组合物。

公开(公告)号：US08575655B2

公开(公告)日：2013-11-05

申请号：US13431328

申请日：2012-03-27

申请人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

发明人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

IPC分类号： H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02612 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。

公开(公告)号：US20130009211A1

公开(公告)日：2013-01-10

申请号：US13616994

申请日：2012-09-14

申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

IPC分类号： H01L29/161 ,  H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。

公开(公告)号：US07776624B2

公开(公告)日：2010-08-17

申请号：US12168945

申请日：2008-07-08

申请人： Ashima B. Chakravarti ,  Judson Robert Holt ,  Jeremy John Kempisty ,  Suk Hoon Ku ,  Woo-Hyeong Lee ,  Amlan Majumdar ,  Ryan Matthew Mitchell ,  Renee Tong Mo ,  Zhibin Ren ,  Dinkar Singh

发明人： Ashima B. Chakravarti ,  Judson Robert Holt ,  Jeremy John Kempisty ,  Suk Hoon Ku ,  Woo-Hyeong Lee ,  Amlan Majumdar ,  Ryan Matthew Mitchell ,  Renee Tong Mo ,  Zhibin Ren ,  Dinkar Singh

IPC分类号： H01L21/00

CPC分类号： H01L21/02532 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/302 ,  H01L21/30604 ,  Y10S438/947 ,  Y10S438/977

摘要： A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.

摘要翻译： 半导体制造方法。 该方法包括提供半导体衬底，其中半导体衬底包括半导体材料。 接下来，去除半导体衬底的顶部。 接下来，在半导体基板上外延生长第一半导体层，其中第一半导体层中的第一半导体材料的第一原子百分比等于半导体衬底中的衬底半导体材料的衬底原子百分比。

公开(公告)号：US07759213B2

公开(公告)日：2010-07-20

申请号：US12189344

申请日：2008-08-11

申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Dominic J. Schepis

发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Dominic J. Schepis

IPC分类号： H01L21/76

CPC分类号： H01L21/02381 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66636 ,  H01L29/7848

摘要： Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.

摘要翻译： 通过蚀刻硅衬底的暴露部分在硅衬底中形成沟槽。 在覆盖要防止沉积含Si：C的材料的区域之后，使用有限的载气流在约550℃至约600℃的温度下，在单晶片室中进行选择性外延，即， 以小于12标准升/分钟的流速，以不依赖于图案的均匀沉积速率沉积含Si：C的区域。 用于Si：C沉积的本发明的选择性外延工艺提供了相对较高的净沉积速率，其中通过X射线衍射验证碳原子并入到取代位置的高质量Si：C晶体。

公开(公告)号：US20090001430A1

公开(公告)日：2009-01-01

申请号：US11771013

申请日：2007-06-29

申请人： Ashima B. Chakravarti ,  Renee T. Mo

发明人： Ashima B. Chakravarti ,  Renee T. Mo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/28176 ,  H01L29/66636 ,  H01L29/7848

摘要： A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate.

摘要翻译： 公开了一种用于半导体结构的电介质元件及其制造方法，该半导体结构包括在衬底的顶表面上形成有栅极的衬底。 衬底和栅极限定栅极和衬底之间的区域中的间隙。 衬底上的至少一部分位于间隙中的指定量的电介质形成基本上防止栅极和衬底之间不必要的电连接的电介质元件。

公开(公告)号：US07361611B2

公开(公告)日：2008-04-22

申请号：US11349233

申请日：2006-02-08

申请人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

发明人： Ashima B. Chakravarti ,  Judson Holt ,  Kevin K. Chan ,  Sadanand V. Deshpande ,  Rangarajan Jagannathan

IPC分类号： H01L21/31

CPC分类号： H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

摘要： Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.

摘要翻译： 在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体，碳前体等）改善了沉积速率和/或使得可以调谐性能 的电影，如调整电影的压力。 此外，在掺杂的氧化硅或掺杂氮化硅或其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关的信号，作为蚀刻停止或用于在蚀刻期间实现控制。

公开(公告)号：US07119016B2

公开(公告)日：2006-10-10

申请号：US10684596

申请日：2003-10-15

申请人： Ashima B. Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Wayne Dibello ,  Ramaseshan Suryanarayanan Iyer

发明人： Ashima B. Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Wayne Dibello ,  Ramaseshan Suryanarayanan Iyer

IPC分类号： H01L21/36

CPC分类号： C23C16/36 ,  C23C16/24 ,  H01L21/02532 ,  H01L21/0262

摘要： A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.

摘要翻译： 至少包含任何组合中的Si，N和C的化合物，例如式（R-NH）4-n-SiX n N的化合物，其中R是烷基 （其可以相同或不同），n为1,2或3，X为H或卤素（例如双叔丁基氨基硅烷（BTBAS））可与硅烷或硅烷衍生物混合 制作一部电影。 可以通过混合硅烷（SiH 4 SO 4）或硅烷衍生物和包括Si，N和C的化合物如BTBAS来生长多晶硅硅膜。 可以通过改变试剂和条件来生长可控地掺杂有碳和/或氮的膜（例如层状膜）。

公开(公告)号：US08563446B2

公开(公告)日：2013-10-22

申请号：US13474790

申请日：2012-05-18

申请人： Ashima B. Chakravarti ,  Jacob B. Dadson ,  Paul J. Higgins ,  Babar A. Khan ,  John J. Moore ,  Christopher C. Parks ,  Rohit S. Takalkar

发明人： Ashima B. Chakravarti ,  Jacob B. Dadson ,  Paul J. Higgins ,  Babar A. Khan ,  John J. Moore ,  Christopher C. Parks ,  Rohit S. Takalkar

IPC分类号： H01L29/02

CPC分类号： H01L27/10867 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/957

摘要： A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

摘要翻译： 为诸如DRAM器件的半导体和/或存储器件提供了用于形成沟槽结构的方法。 在一个实施例中，用于形成沟槽结构的方法包括在半导体衬底中形成沟槽，并且将沟槽的侧壁暴露于含砷气体以在沟槽的侧壁上吸附含砷层。 然后将材料层沉积在沟槽的侧壁上以将含砷层包封在材料层和沟槽的侧壁之间。

公开(公告)号：US20100112762A1

公开(公告)日：2010-05-06

申请号：US12684551

申请日：2010-01-08

申请人： Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C.T. Harley ,  Judson R. Holt

发明人： Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C.T. Harley ,  Judson R. Holt

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/66545 ,  H01L21/0237 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66553

摘要： Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.

摘要翻译： 公开了制造具有设置在半导体结构的衬底的表面上的非外延薄膜的半导体结构的方法。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。