公开(公告)号：US07982244B2

公开(公告)日：2011-07-19

申请号：US12553496

申请日：2009-09-03

申请人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L29/68 ,  H01L29/417 ,  H01L27/105

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

公开(公告)号：US20110250744A1

公开(公告)日：2011-10-13

申请号：US13164931

申请日：2011-06-21

申请人： Atsuhiro SATO ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro SATO ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

公开(公告)号：US08377814B2

公开(公告)日：2013-02-19

申请号：US13164931

申请日：2011-06-21

申请人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

公开(公告)号：US20100052017A1

公开(公告)日：2010-03-04

申请号：US12553496

申请日：2009-09-03

申请人： Atsuhiro SATO ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro SATO ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L29/66 ,  H01L21/4763

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。

公开(公告)号：US09293547B2

公开(公告)日：2016-03-22

申请号：US13237425

申请日：2011-09-20

申请人： Fumitaka Arai ,  Wataru Sakamoto ,  Fumie Kikushima ,  Hiroyuki Nitta

发明人： Fumitaka Arai ,  Wataru Sakamoto ,  Fumie Kikushima ,  Hiroyuki Nitta

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  H01L21/764 ,  H01L27/115 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L29/42336 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

摘要翻译： 根据一个实施例，去除埋在沟槽中的埋入绝缘膜的一部分; 因此，在字线方向上在相邻的浮置栅电极之间形成气隙，并且沿着沟槽以沉没在控制栅电极下方的方式连续地形成气隙。

公开(公告)号：US20120126306A1

公开(公告)日：2012-05-24

申请号：US13238380

申请日：2011-09-21

申请人： Genki KAWAGUCHI ,  Fumitaka Arai ,  Satoshi Nagashima ,  Naoki Kai ,  Wataru Sakamoto ,  Hiroyuki Nitta

发明人： Genki KAWAGUCHI ,  Fumitaka Arai ,  Satoshi Nagashima ,  Naoki Kai ,  Wataru Sakamoto ,  Hiroyuki Nitta

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L29/42376

摘要： According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction.

摘要翻译： 根据一个实施例，存储单元包括电荷存储层。 在字线方向相邻的电荷存储层之间设置第一气隙。 在位线方向相邻的电荷存储层之间提供第二气隙。

公开(公告)号：US08154560B2

公开(公告)日：2012-04-10

申请号：US12468345

申请日：2009-05-19

申请人： Yoshiki Kurokawa ,  Yasuyuki Kudo ,  Hiroyuki Nitta ,  Kazuki Homma ,  Junya Takeda

发明人： Yoshiki Kurokawa ,  Yasuyuki Kudo ,  Hiroyuki Nitta ,  Kazuki Homma ,  Junya Takeda

IPC分类号： G09G5/00 ,  G09G5/02 ,  H04N1/46 ,  H04N1/60 ,  G06T1/00 ,  G06K9/00 ,  G06K9/40

CPC分类号： G09G1/002 ,  G09G3/3655 ,  G09G5/04 ,  G09G5/06 ,  G09G2320/0242 ,  G09G2340/145

摘要： A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

摘要翻译： 本发明的显示驱动电路具有：能够存储初始色域顶点坐标的初始色域 - 顶点坐标存储单元; 能够存储用户目标色域顶点坐标的用户对象色彩 - 顶点坐标存储单元; 饱和扩张系数决定单元，用于基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数; 以及用于基于饱和度膨胀系数扩大显示数据的饱和度的扩展单元。 基于初始和用户目标色域顶点坐标来确定饱和度数据的扩展系数，根据扩展系数扩展显示数据的饱和度。 因此，可以对于每个色域或LC显示面板的R，G和B颜色属性中的每一个来控制饱和度的扩大程度。

公开(公告)号：US08008704B2

公开(公告)日：2011-08-30

申请号：US12372505

申请日：2009-02-17

申请人： Hiroyuki Nitta

发明人： Hiroyuki Nitta

IPC分类号： H01L21/00

CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L23/5222 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. A void part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto. A bottom and two sides of each void part are shielded by the second insulating film, and a top of each void part is shielded by the third insulating film.

摘要翻译： 为了减小半导体存储器件中每个相邻两个字线之间的电容，在每个相邻的两个存储晶体管的栅极之间的间隙中形成第一绝缘膜，其间具有第一栅极绝缘膜，并且在栅极 的选择晶体管和与其相邻的存储晶体管的栅极。 此外，第二绝缘膜形成在第一绝缘膜上，每个存储晶体管的栅极的侧面和面向存储晶体管的选择性晶体管的栅极的一侧。 第三绝缘膜平行于半导体衬底形成以覆盖金属硅化物膜，第一和第二绝缘膜以及第四和第五绝缘膜。 在存储晶体管的每个相邻的两个栅极之间的间隙中以及与选择晶体管的栅极和与其相邻的存储晶体管的栅极之间的空隙中设置空隙部分。 每个空隙部分的底部和两侧被第二绝缘膜屏蔽，并且每个空隙部分的顶部被第三绝缘膜屏蔽。

公开(公告)号：USRE42597E1

公开(公告)日：2011-08-09

申请号：US11980691

申请日：2007-10-31

申请人： Hiroyuki Nitta ,  Hiroyuki Mano ,  Tsutomu Furuhashi ,  Isao Takita ,  Satoru Tsunekawa ,  Toshio Futami ,  Makiko Ikeda

发明人： Hiroyuki Nitta ,  Hiroyuki Mano ,  Tsutomu Furuhashi ,  Isao Takita ,  Satoru Tsunekawa ,  Toshio Futami ,  Makiko Ikeda

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2330/023

摘要： A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.

摘要翻译： 液晶驱动器包括：基于参考电压产生灰度电压的电压发生器;以及用于根据显示数据从产生的灰度级电压中选择一个灰度级电压的输出装置，用于施加反相/非反相控制 基于所选择的灰度级电压，AC开关信号和反转参考电压相对于反转参考电压的所选择的灰度级电压，并且将用于一个和相同显示数据的不同液晶电源电压输出到 液晶面板。

公开(公告)号：US20110038194A1

公开(公告)日：2011-02-17

申请号：US12855151

申请日：2010-08-12

申请人： Takeshi MURATA ,  Yutaka Ishibashi ,  Hiroyuki Nitta

发明人： Takeshi MURATA ,  Yutaka Ishibashi ,  Hiroyuki Nitta

IPC分类号： G11C5/06 ,  G11C11/00

CPC分类号： G11C5/063 ,  G11C11/22 ,  G11C13/0007 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021

摘要： According to one embodiment, a semiconductor storage device includes a plurality of parallel first interconnects extending in a first direction, a plurality of parallel second interconnects which extend in a second direction perpendicular to the first direction and which make a two-level crossing with respect to the first interconnects, and memory cell structures provided in regions where the first interconnects and the second interconnects make two-level crossings, the memory cell structures being connected on one end to the first interconnects and connected on the other end to the second interconnects, the memory cell structure including a variable resistive element and a non-ohmic element which are connected in series, wherein the endmost first interconnect is disconnected in at least one portion.

摘要翻译： 根据一个实施例，半导体存储装置包括在第一方向上延伸的多个平行的第一互连件，多个平行的第二互连件，其沿与第一方向垂直的第二方向延伸，并且相对于 所述第一互连和存储单元结构设置在所述第一互连和所述第二互连构成两级交叉的区域中，所述存储单元结构的一端连接到所述第一互连并在另一端连接到所述第二互连， 存储单元结构包括串联连接的可变电阻元件和非欧姆元件，其中最末端的第一互连件在至少一部分中断开。