公开(公告)号：US20120126306A1

公开(公告)日：2012-05-24

申请号：US13238380

申请日：2011-09-21

申请人： Genki KAWAGUCHI ,  Fumitaka Arai ,  Satoshi Nagashima ,  Naoki Kai ,  Wataru Sakamoto ,  Hiroyuki Nitta

发明人： Genki KAWAGUCHI ,  Fumitaka Arai ,  Satoshi Nagashima ,  Naoki Kai ,  Wataru Sakamoto ,  Hiroyuki Nitta

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L29/42376

摘要： According to one embodiment, a memory cell includes a charge storage layer. A first air gap is provided between charge storage layers adjacent in a word line direction. A second air gap is provided between charge storage layers adjacent in a bit line direction.

摘要翻译： 根据一个实施例，存储单元包括电荷存储层。 在字线方向相邻的电荷存储层之间设置第一气隙。 在位线方向相邻的电荷存储层之间提供第二气隙。

公开(公告)号：US09293547B2

公开(公告)日：2016-03-22

申请号：US13237425

申请日：2011-09-20

申请人： Fumitaka Arai ,  Wataru Sakamoto ,  Fumie Kikushima ,  Hiroyuki Nitta

发明人： Fumitaka Arai ,  Wataru Sakamoto ,  Fumie Kikushima ,  Hiroyuki Nitta

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  H01L21/764 ,  H01L27/115 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234

CPC分类号： H01L29/42336 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

摘要翻译： 根据一个实施例，去除埋在沟槽中的埋入绝缘膜的一部分; 因此，在字线方向上在相邻的浮置栅电极之间形成气隙，并且沿着沟槽以沉没在控制栅电极下方的方式连续地形成气隙。

公开(公告)号：US20120069669A1

公开(公告)日：2012-03-22

申请号：US13237320

申请日：2011-09-20

申请人： Wataru SAKAMOTO ,  Fumitaka Arai

发明人： Wataru SAKAMOTO ,  Fumitaka Arai

IPC分类号： G11C16/10 ,  H01L21/762

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3418 ,  H01L21/28273 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage.

摘要翻译： 公开了一种非易失性半导体存储装置。 该设备包括具有第一存储器单元的单元组和位于第一定向相邻于第一存储单元的第二存储单元，以及编程电路。 第一存储单元用于数据保持，第二存储单元用于调整第一存储单元的阈值电压。 编程电路被配置为通过向第二存储器单元施加电压来对第一存储单元进行编程，以将第一存储单元的阈值电压控制为高于第一阈值电压。

公开(公告)号：US08520443B2

公开(公告)日：2013-08-27

申请号：US13238442

申请日：2011-09-21

申请人： Fumitaka Arai ,  Wataru Sakamoto

发明人： Fumitaka Arai ,  Wataru Sakamoto

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/06 ,  G11C16/3418

摘要： A storage device according to one embodiment includes memory cells which are connected in series in a first direction and are arranged in a matrix by the arranged series connections, and word lines which connect control gates of the memory cells in a second direction perpendicular to the first direction, in which a first interval and a second interval wider than that are alternately repeated for intervals in the second direction between the memory cells. The storage device according to the embodiment comprises a drive unit for writing data in a first cell, then writing data in a second cell which is connected to the same word line as the first cell and is spaced at the first interval in the second direction, then reading the data in the second cell, and reading the data in the first cell with correction based on the read value of the second cell.

摘要翻译： 根据一个实施例的存储装置包括在第一方向上串联连接并且通过排列的串联连接被布置成矩阵的存储单元，以及在垂直于第一方向的第二方向上连接存储单元的控制栅极的字线 方向，其中对于在存储单元之间的第二方向上的间隔交替地重复比其宽的第一间隔和第二间隔。 根据实施例的存储装置包括用于在第一单元中写入数据的驱动单元，然后在连接到与第一单元相同的字线并在第二方向上以第一间隔隔开的第二单元中写入数据， 然后读取第二单元中的数据，并且基于第二单元的读取值来校正第一单元中的数据。

公开(公告)号：US20120025293A1

公开(公告)日：2012-02-02

申请号：US13194131

申请日：2011-07-29

申请人： Wataru Sakamoto ,  Fumitaka Arai

发明人： Wataru Sakamoto ,  Fumitaka Arai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one embodiment, a semiconductor memory device having a memory cells and word lines is provided. The memory cells are formed in a semiconductor layer and arranged in matrix. Each of the memory cells has a floating gate and a control gate. Each plurality of the memory cells is connected in series in a row direction. Each of the word lines is connected to each plurality of the control gates in a column direction. First and second intervals are provided for the memory cells alternately in the column direction. The second interval is larger than the first interval.

摘要翻译： 根据一个实施例，提供了具有存储单元和字线的半导体存储器件。 存储单元形成在半导体层中并且被布置成矩阵。 每个存储单元具有浮动栅极和控制栅极。 每个存储单元中的每一个在行方向串联连接。 每个字线在列方向上连接到每个控制门。 在列方向上交替地为存储单元提供第一和第二间隔。 第二个间隔大于第一个间隔。

公开(公告)号：US08837223B2

公开(公告)日：2014-09-16

申请号：US13600991

申请日：2012-08-31

申请人： Wataru Sakamoto ,  Fumitaka Arai ,  Takashi Kobayashi ,  Ken Komiya ,  Shinichi Sotome ,  Tatsuya Kato

发明人： Wataru Sakamoto ,  Fumitaka Arai ,  Takashi Kobayashi ,  Ken Komiya ,  Shinichi Sotome ,  Tatsuya Kato

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  H01L21/28 ,  H01L29/788 ,  G11C16/10

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/788

摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层， 栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。 控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。

公开(公告)号：US20130235666A1

公开(公告)日：2013-09-12

申请号：US13600991

申请日：2012-08-31

申请人： Wataru Sakamoto ,  Fumitaka Arai ,  Takashi Kobayashi ,  Ken Komiya ,  Shinichi Sotome ,  Tatsuya Kato

发明人： Wataru Sakamoto ,  Fumitaka Arai ,  Takashi Kobayashi ,  Ken Komiya ,  Shinichi Sotome ,  Tatsuya Kato

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L21/28

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11531 ,  H01L29/788

摘要： A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array in which a plurality of NAND cell units are arranged, the NAND cell units including a plurality of memory cells, and select gate transistors, the memory cell including a semiconductor layer, a gate insulating film, a charge accumulation layer, and a control gate; and a control circuit. The control circuit adjusts a write condition of each of the memory cells in accordance with write data to each of the memory cells and memory cells adjacent to the memory cells within the data to be written.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：其中布置多个NAND单元单元的存储单元阵列，包括多个存储单元的NAND单元单元和选择栅极晶体管，所述存储单元包括半导体层， 栅极绝缘膜，电荷蓄积层和控制栅极; 和控制电路。 控制电路根据写入数据将每个存储器单元的写入条件调整到与要写入的数据内的存储单元相邻的存储单元和存储单元。

公开(公告)号：US08537619B2

公开(公告)日：2013-09-17

申请号：US13237320

申请日：2011-09-20

申请人： Wataru Sakamoto ,  Fumitaka Arai

发明人： Wataru Sakamoto ,  Fumitaka Arai

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3418 ,  H01L21/28273 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device is disclosed. The device includes a cell group having a first memory cell and a second memory cell located first directionally adjacent to the first memory cell, and a programming circuit. The first memory cell is used for data retention and the second memory cell is used for adjustment of a threshold voltage of the first memory cell. The programming circuit is configured to program the first memory cell by applying voltage to the second memory cell to control the threshold voltage of the first memory cell to be higher than a first threshold voltage.

摘要翻译： 公开了一种非易失性半导体存储装置。 该设备包括具有第一存储器单元的单元组和位于第一定向相邻于第一存储单元的第二存储单元，以及编程电路。 第一存储单元用于数据保持，第二存储单元用于调整第一存储单元的阈值电压。 编程电路被配置为通过向第二存储器单元施加电压来对第一存储单元进行编程，以将第一存储单元的阈值电压控制为高于第一阈值电压。

公开(公告)号：US08541830B1

公开(公告)日：2013-09-24

申请号：US13601468

申请日：2012-08-31

申请人： Satoshi Nagashima ,  Fumitaka Arai ,  Hisataka Meguro

发明人： Satoshi Nagashima ,  Fumitaka Arai ,  Hisataka Meguro

IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C11/34

CPC分类号： H01L27/088 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/788 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.

摘要翻译： 根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极 下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

公开(公告)号：US08377814B2

公开(公告)日：2013-02-19

申请号：US13164931

申请日：2011-06-21

申请人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

发明人： Atsuhiro Sato ,  Hiroyuki Nitta ,  Fumitaka Arai

IPC分类号： H01L21/28

CPC分类号： H01L27/11524 ,  H01L21/76816 ,  H01L27/11521

摘要： A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

摘要翻译： 半导体存储器件包括具有第一存储器单元和第一选择晶体管的第一块，具有第二存储单元和第二选择晶体管的第二块，并且沿第一方向布置成与第一块相邻，第二选择晶体管被布置为面对 第一选择晶体管，并且通常具有与第一选择晶体管的扩散区，第一互连层，设置在第一和第二块之间的扩散区上并沿第二方向延伸;第二互连层，具有设置成与第一选择晶体管接触的第一部分 第一互连层的上部并且延伸到第一互连层外部的部分，以及第二部分，其在第二方向上延伸并且在第一互连层上的部分外部的部分连接到第一部分。