公开(公告)号：US11848039B2

公开(公告)日：2023-12-19

申请号：US17227294

申请日：2021-04-10

申请人： Avalanche Technology, Inc.

发明人： Zhiqiang Wei ,  Kimihiro Satoh ,  Woojin Kim ,  Zihui Wang

IPC分类号： G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC分类号： G11C11/161 ,  H10B61/10 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

摘要： The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

公开(公告)号：US20220383920A9

公开(公告)日：2022-12-01

申请号：US17227294

申请日：2021-04-10

申请人： Avalanche Technology, Inc.

发明人： Zhiqiang Wei ,  Kimihiro Satoh ,  Woojin Kim ,  Zihui Wang

IPC分类号： G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

摘要： The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

公开(公告)号：US20210312964A1

公开(公告)日：2021-10-07

申请号：US17227294

申请日：2021-04-10

申请人： Avalanche Technology, Inc.

发明人： Zhiqiang Wei ,  Kimihiro Satoh ,  Woojin Kim ,  Zihui Wang

IPC分类号： G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

摘要： The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

公开(公告)号：US10522590B2

公开(公告)日：2019-12-31

申请号：US15921552

申请日：2018-03-14

申请人： Avalanche Technology, Inc.

发明人： Kimihiro Satoh ,  Hongxin Yang

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10

摘要： The present invention is directed to a memory device including a magnetic memory element; a horizontal conductive line disposed above the magnetic memory element; a bottom electrode formed beneath the magnetic memory element and having a top, first and second sides that are opposite to each other; a first vertical conductive line formed adjacent to the first side of the bottom electrode with a first volatile switching layer and a first electrode layer interposed therebetween; and a second vertical conductive line formed adjacent to the second side of the bottom electrode with a second volatile switching layer and a second electrode layer interposed therebetween. The magnetic memory element is electrically connected to the horizontal conductive line at one end and to the bottom electrode at the other end.

公开(公告)号：US10008540B2

公开(公告)日：2018-06-26

申请号：US15586638

申请日：2017-05-04

申请人： Avalanche Technology, Inc.

发明人： Parviz Keshtbod ,  Xiaobin Wang ,  Kimihiro Satoh ,  Zihui Wang ,  Huadong Gan

IPC分类号： H01L27/22 ,  H01L43/08

CPC分类号： H01L27/228 ,  H01L43/08

摘要： The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.

公开(公告)号：US09373663B2

公开(公告)日：2016-06-21

申请号：US14033374

申请日：2013-09-20

申请人： Avalanche Technology Inc.

发明人： Kimihiro Satoh ,  Yiming Huai

IPC分类号： H01L27/112 ,  H01L27/22

CPC分类号： H01L27/224 ,  H01L27/222

摘要： The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.

摘要翻译： 本发明涉及一种在外围电路中具有最小化存储单元大小的通孔接合焊盘的存储器件。 具有本发明特征的器件包括至少包括磁性隧道结（MTJ）元件的外围电路区域和磁性存储单元区域。 外围电路区域包括形成在其中的基板和底部触点; 包括形成在底部触点顶部的第一磁性层结构的层站焊盘和通过绝缘隧道结层与第一磁性层结构隔开的第二磁性层结构，其中绝缘隧道结层和第二磁性层结构 具有彼此对准的开口; 以及通过部分地嵌入在所述着陆焊盘中并且通过所述开口直接耦合到所述第一磁性层结构的通孔。

公开(公告)号：US20160064650A1

公开(公告)日：2016-03-03

申请号：US14831546

申请日：2015-08-20

申请人： Avalanche Technology, Inc.

发明人： Xiaobin Wang ,  Parviz Keshtbod ,  Kimihiro Satoh ,  Zihui Wang ,  Huadong Gan

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/08

CPC分类号： H01L27/228 ,  H01L43/08

摘要： The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current. The variable magnetization direction of the magnetic free layer structure is not switched by the comparison current.

摘要翻译： 本发明涉及一种包括具有伪不变磁化方向的磁性比较层结构的自旋 - 轨道学装置。 磁性自由层结构，其可变磁化方向可以通过在磁比较层结构和磁自由层结构之间的开关电流来切换; 介于磁比较层结构和磁自由层结构之间的绝缘隧道结层; 以及与磁性比较层结构相邻形成的非磁性横向偏振层。 可以通过使比较电流沿着与横向偏振层的层平面大致平行的方向通过横向偏振层来切换磁性比较层结构的伪不变磁化方向。 磁性比较层结构的伪不变磁化方向不被切换电流切换。 磁性层结构的可变磁化方向不被比较电流切换。

公开(公告)号：US09029822B2

公开(公告)日：2015-05-12

申请号：US13843644

申请日：2013-03-15

申请人： Avalanche Technology Inc.

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Dong Ha Jung

IPC分类号： H01L27/112 ,  H01L27/24 ,  H01L27/115 ,  H01L27/22

CPC分类号： H01L27/11273 ,  H01L27/11556 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

摘要： Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.

摘要翻译： 描述了以能够缩小到4F2的单位面积制造的电阻式存储单元阵列，其中F是技术节点中的最小特征尺寸。 一对电池中的存储单元通常包括在硅衬底中形成的沟槽底部的一对掩埋源。 源线与相邻单元共享。 一对栅电极在沟槽的侧壁上提供垂直沟道。 掩埋字线连接覆盖源极的侧壁上的栅极的底部，其中字线在阵列的末端环绕。 通过在对沟槽进行图案化之前，通过注入/掺杂硅的表面来形成与栅极自对准的漏极。 在漏极的顶部形成接触，并且在触点上制造电阻式存储元件。

公开(公告)号：US08803200B2

公开(公告)日：2014-08-12

申请号：US14038582

申请日：2013-09-26

申请人： Avalanche Technology Inc.

发明人： Kimihiro Satoh ,  Ebrahim Abedifard

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L43/02 ,  H01L27/22

CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L29/66666 ,  H01L29/7827

摘要： A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.

摘要翻译： 形成磁存储单元，其包括用于在操作中访问MTJ的磁隧道结（MTJ）和存取晶体管。 形成在硅衬底上的存取晶体管包括栅极，漏极和源极，其栅极位置基本上垂直于硅衬底的平面，由此埋入栅极并允许硅衬底上的更多表面积形成额外的存储器 细胞。

公开(公告)号：US20140170776A1

公开(公告)日：2014-06-19

申请号：US14096016

申请日：2013-12-04

申请人： Avalanche Technology Inc.

发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Jing Zhang ,  Benjamin Chen ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Yuchen Zhou

IPC分类号： H01L43/12

CPC分类号： H01L43/12

摘要： Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

摘要翻译： 描述了使用离子束蚀刻（IBE）对MRAM单元记忆元件的制造方法。 在本发明的实施例中，使用诸如RIE或磁化感应耦合等离子体（MICP）的反应蚀刻用一个掩模来蚀刻顶部电极和MTJ主体以提高选择性，然后使用如在各种替代实施例中所规定的IBE蚀刻底部电极 包括在IBE之前沉积的入射角，晶片旋转速率曲线和可选的钝化层的选择。 根据本发明的IBE通过使用由第一蚀刻阶段产生的层堆叠作为掩模来蚀刻底部电极而不需要附加掩模。 这使得底部电极与MTJ自对准。 国际教育局还实现了MTJ侧墙清洁，无需额外的步骤。