公开(公告)号：US09099970B2

公开(公告)日：2015-08-04

申请号：US13909387

申请日：2013-06-04

Applicant: Broadcom Corporation

Inventor： Junhua Tan ,  Hui Pan ,  Karim Vincent Abdelhalim ,  Mostafa Mohammad Hany Ali Hammad ,  Yuan Yao

IPC: H03F3/45

CPC classification number: H03F3/45183 ,  H03F3/45941 ,  H03F3/45959 ,  H03F2203/45466 ,  H03F2203/45641 ,  H03F2203/45642

Abstract: An output stage of a differential line driver generates a differential output signal. A common-mode component of the differential output signal is decoupled from the differential output signal using a common-mode voltage sense. The common-mode component of the differential output signal is provided to a capacitor that is coupled between the output stage and the common-mode voltage sense.

Abstract translation: 差分线路驱动器的输出级产生差分输出信号。 使用共模电压感测，差分输出信号的共模分量与差分输出信号去耦。 差分输出信号的共模分量被提供给耦合在输出级和共模电压检测之间的电容器。

公开(公告)号：US09356616B1

公开(公告)日：2016-05-31

申请号：US14816387

申请日：2015-08-03

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Xin Jin ,  Chia-Jen Hsu

IPC: H03M1/14 ,  H03M1/44 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/445 ,  H03M1/141 ,  H03M1/144 ,  H03M1/145 ,  H03M1/204 ,  H03M1/46

Abstract: A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.

Abstract translation: 一个多位每周期逐次逼近寄存器（SAR）模数转换器（ADC）可以对输入信号进行采样，以包含信号的收缩子范围连续近似采样信号，并输出对应于 子范围 子范围级可以通过在绑定子范围的一对过零信号之间进行采样和内插来在子范围上继续量化。 过零信号可以取自SAR前置放大器输出。 子范围过程可以在多个阶段递归流水线以增加吞吐量和效率。

公开(公告)号：US09356593B2

公开(公告)日：2016-05-31

申请号：US14266465

申请日：2014-04-30

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Karim Abdelhalim

IPC: H03M1/12 ,  H03K17/08 ,  H03M1/38 ,  H03M1/16 ,  H03M1/46

CPC classification number: H03K17/08 ,  H03M1/1245 ,  H03M1/168 ,  H03M1/38 ,  H03M1/468

Abstract: Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations. Based on the value of the signal representations, a state machine controls each of the switches to apply reference signals to the input buffers, during a second operation phase, and to iteratively generate additional signal representations and provide a digital signal that corresponds to the analog input signal.

Abstract translation: 为模数转换器（ADC）提供系统，装置和方法，例如逐次逼近寄存器（SAR）ADC和利用分布式虚拟地交换（DVS）的流水线ADC。 DVS电路和系统接收通过参考开关提供给缓冲器输入端的输入信号缓冲器的参考信号输入。 输入信号缓冲器和相应的开关分配到缩放副本中，每个复本在第一操作阶段通过输入信号开关接收模拟输入信号，并连接到相应的分布式电容器的顶板。 电容器的底板被采样以提供模拟输入信号表示。 基于信号表示的值，状态机控制每个开关以在第二操作阶段期间将参考信号施加到输入缓冲器，并且迭代地产生附加的信号表示并提供对应于模拟输入的数字信号 信号。

公开(公告)号：US09281967B2

公开(公告)日：2016-03-08

申请号：US14090512

申请日：2013-11-26

Applicant: Broadcom Corporation

Inventor： Yuan Yao ,  Jing Wang ,  Junhua Tan ,  Mostafa Mohammad Hany Ali Hammad ,  Hui Pan

IPC: G11C8/00 ,  H04L25/02 ,  H03F3/21 ,  H03F3/45

CPC classification number: H04L25/0272 ,  H03F3/211 ,  H03F3/45179 ,  H03F2200/456 ,  H03F2203/45311 ,  H03F2203/45356 ,  H03F2203/45394 ,  H03F2203/45481 ,  H04L25/026

Abstract: Aspects of rail-to-rail line drivers using differential cascode bootstrapping are described. In one embodiment, a differential line driver includes first and second differential driver output legs. The first output leg includes a first p-type cascode stack and a first n-type cascode stack, and the second output leg includes a second p-type cascode stack and a second n-type cascode stack. The differential line driver also includes a differential cascode bootstrap circuit arrangement coupled to an output of the differential line driver. More particularly, the differential cascode bootstrap circuit arrangement is coupled between the first and second differential output driver legs and the output of the differential line driver. According to aspects of the embodiments described herein, differential line drivers with overvoltage protection and rail-to-rail output swings may be achieved. Further, the differential line drivers may be generally smaller, with cascode stack transistors of reduced in size.

Abstract translation: 描述了使用差分共源共栅自举的轨到轨线路驱动器的方面。 在一个实施例中，差分线路驱动器包括第一和第二差分驱动器输出支路。 第一输出支路包括第一p型共源共栅堆叠和第一n型共源共栅堆叠，并且第二输出支路包括第二p型共源共栅堆叠和第二n型共源共栅堆叠。 差分线路驱动器还包括耦合到差分线路驱动器的输出的差分共源共栅引导电路装置。 更具体地，差分共源共栅自举电路布置耦合在第一和第二差分输出驱动器支路和差分线路驱动器的输出之间。 根据本文所描述的实施例的方面，可以实现具有过压保护和轨到轨输出摆幅的差分线路驱动器。 此外，差分线路驱动器可以通常更小，其中级联叠层晶体管的尺寸减小。

公开(公告)号：US20150137887A1

公开(公告)日：2015-05-21

申请号：US14090512

申请日：2013-11-26

Applicant: Broadcom Corporation

Inventor： Yuan Yao ,  Jing Wang ,  Junhua Tan ,  Mostafa Mohammad Hany Ali Hammad ,  Hui Pan

IPC: H03K3/01

CPC classification number: H04L25/0272 ,  H03F3/211 ,  H03F3/45179 ,  H03F2200/456 ,  H03F2203/45311 ,  H03F2203/45356 ,  H03F2203/45394 ,  H03F2203/45481 ,  H04L25/026

Abstract: Aspects of rail-to-rail line drivers using differential cascode bootstrapping are described. In one embodiment, a differential line driver includes first and second differential driver output legs. The first output leg includes a first p-type cascode stack and a first n-type cascode stack, and the second output leg includes a second p-type cascode stack and a second n-type cascode stack. The differential line driver also includes a differential cascode bootstrap circuit arrangement coupled to an output of the differential line driver. More particularly, the differential cascode bootstrap circuit arrangement is coupled between the first and second differential output driver legs and the output of the differential line driver. According to aspects of the embodiments described herein, differential line drivers with overvoltage protection and rail-to-rail output swings may be achieved. Further, the differential line drivers may be generally smaller, with cascode stack transistors of reduced in size.

Abstract translation: 描述了使用差分共源共栅自举的轨到轨线路驱动器的方面。 在一个实施例中，差分线路驱动器包括第一和第二差分驱动器输出支路。 第一输出支路包括第一p型共源共栅堆叠和第一n型共源共栅堆叠，并且第二输出支路包括第二p型共源共栅堆叠和第二n型共源共栅堆叠。 差分线路驱动器还包括耦合到差分线路驱动器的输出的差分共源共栅引导电路装置。 更具体地，差分共源共栅自举电路布置耦合在第一和第二差分输出驱动器支路和差分线路驱动器的输出之间。 根据本文所描述的实施例的方面，可以实现具有过压保护和轨到轨输出摆幅的差分线路驱动器。 此外，差分线路驱动器可以通常更小，其中级联叠层晶体管的尺寸减小。

公开(公告)号：US20150071136A1

公开(公告)日：2015-03-12

申请号：US14038928

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Mostafa Mohammad Hany Ali Hammad ,  Yuan Yao

IPC: H04L5/14 ,  H04B3/23

CPC classification number: H04L5/1415 ,  H04B3/23 ,  H04L25/0278 ,  H04L25/028

Abstract: A system includes a full-duplex driver to drive signals on a load. A hybrid element connected with the full-duplex driver controls a flow of transmission and receipt of the signals. A gain control element connected with the full-duplex driver tunes a transconductance of the full-duplex driver to match an impedance of the load. The controlled gain is based on a leakage voltage value of the full-duplex driver.

Abstract translation: 系统包括一个全双工驱动器来驱动负载上的信号。 与全双工驱动器连接的混合元件控制信号的传输和接收。 与全双工驱动器连接的增益控制元件调整全双工驱动器的跨导以匹配负载的阻抗。 受控增益基于全双工驱动器的泄漏电压值。

公开(公告)号：US08866552B2

公开(公告)日：2014-10-21

申请号：US13721786

申请日：2012-12-20

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Yuan Yao ,  Mostafa Hammad ,  Karim Vincent Abdelhalim ,  Junhua Tan ,  Ichiro Fujimori

IPC: H03F3/45 ,  H03F3/68

CPC classification number: H03F3/45179 ,  H03F3/45183 ,  H03F3/45632 ,  H03F3/68 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45648

Abstract: Disclosed are various embodiments of a current-mode line driver that may facilitate transmitting signals to a load. The current-mode line driver may comprise a common-mode current sense element that provides a signal corresponding to the common-mode output current of the line driver. A transconductance element receives the signal from the common-mode current sense element and provides a compensating current that is based at least in part on the signal. The compensating current may reduce the common-mode output current of the line driver.

Abstract translation: 公开了可以有助于将信号发送到负载的电流模式线路驱动器的各种实施例。 电流模式线路驱动器可以包括提供对应于线路驱动器的共模输出电流的信号的共模电流检测元件。 跨导元件从共模电流检测元件接收信号，并提供至少部分地基于该信号的补偿电流。 补偿电流可能会降低线路驱动器的共模输出电流。

公开(公告)号：US20160161972A1

公开(公告)日：2016-06-09

申请号：US14601062

申请日：2015-01-20

Applicant: BROADCOM CORPORATION

Inventor： Junhua TAN ,  Yuan Yao ,  Jing Wang ,  Hui Pan

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A scaled voltage supply to supply voltage biases to circuits in voltage zones. The scaled voltage supply includes a master voltage corresponding to a voltage drop across a master-upper rail having a voltage Vdd and a master-lower rail having a voltage Vss=0. Further, the supply includes a voltage-divider network dividing the master voltage Vdd into intermediate voltages αVdd, βVdd, etc., wherein α and β are predetermined constants. These intermediate voltages scale with the master voltage and are supplied to the voltage zones using non-invasive soft rails. In one implementation the soft rails use voltage mirrors to supply the intermediate voltages to the circuits within voltage zones.

Abstract translation: 电压电压的电压供应电压偏压到电压区中的电路。 缩放的电压源包括对应于具有电压Vdd的主 - 上导轨上的电压降的主电压和具有电压Vss = 0的主 - 下导轨。 此外，电源包括将主电压Vdd分为中间电压αVdd，＆amp; Bgr; Vdd等的分压网络，其中α和bgr; 是预定常数。 这些中间电压与主电压成比例，并使用非侵入式软轨提供给电压区。 在一个实施方案中，软轨使用电压镜将中间电压提供给电压区内的电路。

公开(公告)号：US09459646B2

公开(公告)日：2016-10-04

申请号：US14601062

申请日：2015-01-20

Applicant: BROADCOM CORPORATION

Inventor： Junhua Tan ,  Yuan Yao ,  Jing Wang ,  Hui Pan

IPC: G05F3/02 ,  G05F1/10 ,  G05F3/26

CPC classification number: G05F3/262

Abstract: A scaled voltage supply to supply voltage biases to circuits in voltage zones. The scaled voltage supply includes a master voltage corresponding to a voltage drop across a master-upper rail having a voltage Vdd and a master-lower rail having a voltage Vss=0. Further, the supply includes a voltage-divider network dividing the master voltage Vdd into intermediate voltages αVdd, βVdd, etc., wherein α and β are predetermined constants. These intermediate voltages scale with the master voltage and are supplied to the voltage zones using non-invasive soft rails. In one implementation the soft rails use voltage mirrors to supply the intermediate voltages to the circuits within voltage zones.

Abstract translation: 电压电压的电压供应电压偏压到电压区中的电路。 缩放的电压源包括对应于具有电压Vdd的主 - 上导轨上的电压降的主电压和具有电压Vss = 0的主 - 下导轨。 此外，电源包括将主电压Vdd分为中间电压αVdd，βVdd等的分压网络，其中α和β是预定常数。 这些中间电压与主电压成比例，并使用非侵入式软轨提供给电压区。 在一个实施方案中，软轨使用电压镜将中间电压提供给电压区内的电路。

公开(公告)号：US09419779B2

公开(公告)日：2016-08-16

申请号：US14038928

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Mostafa Mohammad Hany Ali Hammad ,  Yuan Yao

IPC: H04B1/38 ,  H04L5/16 ,  H04L5/14 ,  H04B3/23 ,  H04L25/02

CPC classification number: H04L5/1415 ,  H04B3/23 ,  H04L25/0278 ,  H04L25/028

Abstract: A system includes a full-duplex driver to drive signals on a load. A hybrid element connected with the full-duplex driver controls a flow of transmission and receipt of the signals. A gain control element connected with the full-duplex driver tunes a transconductance of the full-duplex driver to match an impedance of the load. The controlled gain is based on a leakage voltage value of the full-duplex driver.

Abstract translation: 系统包括一个全双工驱动器来驱动负载上的信号。 与全双工驱动器连接的混合元件控制信号的传输和接收。 与全双工驱动器连接的增益控制元件调整全双工驱动器的跨导以匹配负载的阻抗。 受控增益基于全双工驱动器的泄漏电压值。