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    Cpu remote snoop filtering mechanism for field programmable gate array
    1.
    发明申请
    Cpu remote snoop filtering mechanism for field programmable gate array 审中-公开

    公开(公告)号：US20170185515A1

    公开(公告)日：2017-06-29

    申请号：US14998298

    申请日：2015-12-26

    申请人： Bahaa Fahim ,  Samuel D. Strom ,  George H. Huang ,  Vedaraman Geetha ,  Yen-Cheng Liu

    发明人： Bahaa Fahim ,  Samuel D. Strom ,  George H. Huang ,  Vedaraman Geetha ,  Yen-Cheng Liu

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F12/084 ,  G06F12/0891 ,  G06F2212/621

    摘要： Apparatus and methods implementing a Remote Snoop Filter (“RSF”) for reducing unnecessary snoops to one or more Field Programmable Gate Arrays (“FPGAs”) in a hardware system by tracking the address and state of each cache line cached in the FPGA's cache. The apparatus include one or more processors, one or more FPGAs, and a system memory. Each processor further comprises a Caching and Home Agent (“CHA”), an L3 or Last Level Cache (“LLC”), and one or more cores wherein each core contains a core cache. The CHA implements and manages an RSF which tracks the address and state of each cache line stored in the one or more FPGAs. The hit/miss result from an RSF lookup is used by the CHA to determine whether or not to filter snoops to the FPGAs. A cache line miss in the RSF indicates that the requested cache line is not in any of the FPGAs and thus no snoop to the FPGA should be issued. This ensures that the FPGAs are generally not snooped unless necessary.

    METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTION HANDLING IN A PROCESSOR
    3.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTION HANDLING IN A PROCESSOR 有权
    用于优化处理器中的高速缓存存储器交易处理的方法，装置和系统

    公开(公告)号：US20160283382A1

    公开(公告)日：2016-09-29

    申请号：US14669248

    申请日：2015-03-26

    申请人： Bahaa Fahim ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Min Huang

    发明人： Bahaa Fahim ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Min Huang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0855 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/27 ,  G06F2212/621 ,  Y02D10/13

    摘要： In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括耦合到核心和高速缓冲存储器的缓存归属代理（CHA），并且包括具有高速缓存流水线和具有归属代理流水线的归属代理的高速缓存控制器。 CHA可以：在归属代理流程中接收来自外部代理的响应于高速缓冲存储器中的数据的遗漏的信息; 从归属代理流水线向数据的请求者发出全局排序信号，以通知请求者接收数据; 并向缓存流水线报告全局排序信号的发布，以防止缓存流水线向请求者发出全局排序信号。 描述和要求保护其他实施例。

    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory
    4.
    发明申请
    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
    包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存

    公开(公告)号：US20150186275A1

    公开(公告)日：2015-07-02

    申请号：US14142045

    申请日：2013-12-27

    申请人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    发明人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0888

    摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.

    摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理核心包括存储器控制器上方的多个缓存级别。 处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。 所述状态信息包括包含状态和不包含状态中的所选择的状态。 包含状态表示在内存中存在高速缓存行的副本或版本。 不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。 逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为 在包容性状态。

    CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS
    8.
    发明申请
    CACHE COHERENCY APPARATUS AND METHOD MINIMIZING MEMORY WRITEBACK OPERATIONS 有权
    高速缓存设备和方法最小化存储器写回操作

    公开(公告)号：US20150178206A1

    公开(公告)日：2015-06-25

    申请号：US14136131

    申请日：2013-12-20

    申请人： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

    发明人： Jeffrey D. Chamberlain ,  Vedaraman Geetha ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Adrian C. Moga ,  Herbert H. Hum ,  Sailesh Kottapalli

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0817 ,  G06F12/0815

    摘要： An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.

    摘要翻译： 一种用于减少或消除写回操作的设备和方法。 例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

    DYNAMICALLY ROUTING DATA RESPONSES DIRECTLY TO REQUESTING PROCESSOR CORE
    9.
    发明申请
    DYNAMICALLY ROUTING DATA RESPONSES DIRECTLY TO REQUESTING PROCESSOR CORE 有权
    动态路由数据的响应直接要求处理器核心

    公开(公告)号：US20130007046A1

    公开(公告)日：2013-01-03

    申请号：US13175772

    申请日：2011-07-01

    申请人： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

    发明人： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

    IPC分类号： G06F17/30

    CPC分类号： G06F13/4022

    摘要： Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

    摘要翻译： 描述了将数据响应直接动态地路由到请求处理器核心的方法和装置。 在一个实施例中，响应于数据请求返回的数据将基于存储在路由表中的信息直接发送到请求代理。 还公开了其他实施例。

    ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES
    10.
    发明申请
    ALLOCATION AND WRITE POLICY FOR A GLUELESS AREA-EFFICIENT DIRECTORY CACHE FOR HOTLY CONTESTED CACHE LINES 有权
    用于高速缓存高速缓存线路的无障碍区域高效目录的分配和写入策略

    公开(公告)号：US20120079214A1

    公开(公告)日：2012-03-29

    申请号：US12890649

    申请日：2010-09-25

    申请人： Adrian C. Moga ,  Malcom Mandviwalla ,  Vedaraman Geetha ,  Herbert H. Hum

    发明人： Adrian C. Moga ,  Malcom Mandviwalla ,  Vedaraman Geetha ,  Herbert H. Hum

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0831 ,  G06F12/082 ,  G06F2212/2542

    摘要： Methods and apparatus relating to allocation and/or write policy for a glueless area-efficient directory cache for hotly contested cache lines are described. In one embodiment, a directory cache stores data corresponding to a caching status of a cache line. The caching status of the cache line is stored for each of a plurality of caching agents in the system. An write-on-allocate policy is used for the directory cache by using a special state (e.g., snoop-all state) that indicates one or more snoops are to be broadcasted to all agents in the system. Other embodiments are also disclosed.

    摘要翻译： 描述与用于热挑战的高速缓存行的无胶带区域高效目录高速缓存的分配和/​​或写入策略有关的方法和装置。 在一个实施例中，目录高速缓存存储与高速缓存行的高速缓存状态对应的数据。 为系统中的多个缓存代理中的每一个存储缓存行的高速缓存状态。 通过使用指示要广播到系统中的所有代理的一个或多个窥探的特殊状态（例如，窥探全状态），对目录高速缓存使用写入分配策略。 还公开了其他实施例。