公开(公告)号：US06417793B1

公开(公告)日：2002-07-09

申请号：US09578838

申请日：2000-05-25

申请人： Alex R. Bugeja ,  Bang-Sup Song

发明人： Alex R. Bugeja ,  Bang-Sup Song

IPC分类号： H03M166

CPC分类号： H03M1/1057 ,  H03M1/0872 ,  H03M1/742

摘要： A track and attenuate (T/A) circuit for use with switched current source DACs is connected across the DAC's differential current outputs. The T/A circuit includes three attenuate switches: first and second single-ended switches which connect the positive and negative sides of the differential output, respectively, to signal ground, and a third, differential switch which connects the positive and negative output lines together. The three attenuate switches are closed simultaneously during a portion of each cycle of the DAC's sample clock, to attenuate the DAC's current outputs while the outputs of the switched current sources are settling—thereby preventing dynamic nonlinearities from being introduced into the differential output current. When properly sized, the three attenuate switches (when closed) reduce the differential output current to near zero and lower the common mode voltage between the positive and negative output lines, significantly improving the DAC's dynamic linearity.

摘要翻译： 用于开关电流源DAC的轨道和衰减（T / A）电路连接在DAC差分电流输出端。 T / A电路包括三个衰减开关：第一和第二单端开关，分别将差分输出的正侧和负极连接到信号地，以及第三个差分开关，将正和负输出线连接在一起 。 三个衰减开关在DAC采样时钟的每个周期的一部分期间同时闭合，以在开关电流源的输出稳定时衰减DAC的电流输出，从而防止动态非线性被引入差分输出电流。 当尺寸合适时，三个衰减开关（闭合时）将差分输出电流降至接近零，降低正负输出线之间的共模电压，显着提高DAC的动态线性度。

公开(公告)号：US06331830B1

公开(公告)日：2001-12-18

申请号：US09631596

申请日：2000-08-03

申请人： Bang-Sup Song ,  Alex R. Bugeja

发明人： Bang-Sup Song ,  Alex R. Bugeja

IPC分类号： H03M110

CPC分类号： H03M1/1057 ,  H03M1/1009 ,  H03M1/742

摘要： A self-trimming current source for used in a switched current source DAC is made from a fixed current source and a variable current source, which are connected in parallel to provide a total output current. The total output current is automatically calibrated by temporarily switching one side of the self-trimming current source to a measurement circuit. Based on the measured value, the variable current source is adjusted to make the total output current equal to a predetermined value. The fixed current source is implemented with a complementary pair of field-effect transistors (FETs) connected in a cascode connection, with the two drain terminals presenting high impedances to the circuitry to which they are connected. A DAC typically includes a plurality of self-trimming current sources, each of which is calibrated during each DAC conversion cycle.

摘要翻译： 用于开关电流源DAC的自整流电流源由固定电流源和可变电流源制成，其并联连接以提供总输出电流。 通过将自整定电流源的一侧临时切换到测量电路，自动校准总输出电流。 基于测量值，调节可变电流源以使总输出电流等于预定值。 固定电流源通过在共源共栅连接中连接的互补的一对场效应晶体管（FET）来实现，两个漏极端子对它们所连接的电路呈现高阻抗。 DAC典型地包括多个自修整电流源，每个电流源在每个DAC转换周期期间被校准。

公开(公告)号：US07453291B2

公开(公告)日：2008-11-18

申请号：US11222227

申请日：2005-09-08

申请人： Bang-Sup Song

发明人： Bang-Sup Song

IPC分类号： H03K5/00

CPC分类号： H03K17/063 ,  G11C27/02 ,  G11C27/024 ,  G11C27/026

摘要： Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of a switch that controls track and hold circuit sampling. In a modified embodiment, capacitive boost is omitted and the feedback amplifier provides the signal-dependent threshold voltage boost. In another embodiment, a boost capacitor and a diode connected transistor provide the signal-dependent threshold voltage boost. In a modified embodiment, capacitive boost is omitted and the diode connected transistor provides the signal-dependent threshold voltage.

摘要翻译： 提供栅极升压以解决CMOS T / H电路中的非线性阈值电压变化的电路。 在本发明的实施例中，升压电容器和反馈放大器将信号相关阈值电压加到控制跟踪和保持电路采样的开关的开关栅极过驱动电压上。 在修改的实施例中，省略了电容性升压，并且反馈放大器提供依赖于信号的阈值电压。 在另一个实施例中，升压电容器和二极管连接晶体管提供依赖于信号的阈值电压升压。 在修改的实施例中，省略了电容性升压，并且二极管连接的晶体管提供依赖于信号的阈值电压。

公开(公告)号：US20060049857A1

公开(公告)日：2006-03-09

申请号：US11222227

申请日：2005-09-08

申请人： Bang-Sup Song

发明人： Bang-Sup Song

IPC分类号： G11C27/02

CPC分类号： H03K17/063 ,  G11C27/02 ,  G11C27/024 ,  G11C27/026

摘要： Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of a switch that controls track and hold circuit sampling. In a modified embodiment, capacitive boost is omitted and the feedback amplifier provides the signal-dependent threshold voltage boost. In another embodiment, a boost capacitor and a diode connected transistor provide the signal-dependent threshold voltage boost. In a modified embodiment, capacitive boost is omitted and the diode connected transistor provides the signal-dependent threshold voltage.

摘要翻译： 提供栅极升压以解决CMOS T / H电路中的非线性阈值电压变化的电路。 在本发明的实施例中，升压电容器和反馈放大器将信号相关阈值电压加到控制跟踪和保持电路采样的开关的开关栅极过驱动电压上。 在修改的实施例中，省略了电容性升压，并且反馈放大器提供依赖于信号的阈值电压。 在另一个实施例中，升压电容器和二极管连接晶体管提供依赖于信号的阈值电压升压。 在修改的实施例中，省略了电容性升压，并且二极管连接的晶体管提供依赖于信号的阈值电压。

公开(公告)号：US5600186A

公开(公告)日：1997-02-04

申请号：US350020

申请日：1994-11-29

申请人： Won-Chul Song ,  Chang-Jun Oh ,  Jong-Ryul Lee ,  Hae-Wook Choi ,  Bang-Sup Song

发明人： Won-Chul Song ,  Chang-Jun Oh ,  Jong-Ryul Lee ,  Hae-Wook Choi ,  Bang-Sup Song

IPC分类号： G05F1/10 ,  H03M1/36 ,  H03M1/74 ,  H01H47/00

CPC分类号： H03M1/361 ,  Y10T307/826

摘要： A capacitor type voltage divider circuit is disclosed. The divider has a plurality of reference voltage signals applied from an external source. A plurality of switching sections are provided for switching the reference voltage signals from the source in response to first and second clock signals. A plurality of dividing sections are provided which are each comprised of two capacitors for dividing the voltage signals from the switching section into a predetermined value. With the dividing circuit, precise levels of reference voltage signals are obtained and power consumption is low without an increase in size or lowering of operational speed.

摘要翻译： 公开了一种电容式分压电路。 分压器具有从外部源施加的多个参考电压信号。 多个开关部分被提供用于响应于第一和第二时钟信号从源极切换参考电压信号。 提供多个分割部分，每个分割部分包括用于将来自切换部分的电压信号分成预定值的两个电容器。 通过分频电路，可以获得精确的参考电压信号，并且功耗低，而不会增加尺寸或降低运行速度。

公开(公告)号：US06714886B2

公开(公告)日：2004-03-30

申请号：US10207470

申请日：2002-07-29

申请人： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

发明人： Eric C. Sung ,  Kantilal Bacrania ,  Hsin-Shu Chen ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M112

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

摘要翻译： 一种用于校准具有包括Σ-Δ转换器，计数器，存储器，调整逻辑，DAC，一对补偿电容器和一对电流 - 电压（I / V）转换器的补偿输入的放大器的补偿系统。 转换器将偏移电压转换为位流。 计数器存储表示输出偏移量的和值。 存储器存储数字偏置值。 调整逻辑基于和值确定调整值，并根据调整值调整存储的数字偏置值。 DAC将数字偏置值转换为差分偏置电流。 补偿电容器将补偿电压施加到放大器的补偿输入。 I / V转换器使用差分偏置电流对补偿电容器充电。 调整逻辑可以使用上限和下限阈值，并且在每个补偿周期内将数字偏置值调整一个LSB​​。

公开(公告)号：US06731155B2

公开(公告)日：2004-05-04

申请号：US10308775

申请日：2002-12-03

申请人： J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

发明人： J. Mikko Hakkarainen ,  Kantilal Bacrania ,  Eric C. Sung ,  Hsin-Shu Chen ,  Bang-Sup Song ,  Mario Sanchez

IPC分类号： H03K1716

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

摘要翻译： 双泵电路，包括传输门和双电荷泵。 传输门包括一个p沟道晶体管和一个n沟道晶体管，每个具有一个控制端子和一对电流端子，耦合在一个双泵输入端和一个双泵输出端之间。 双电荷泵包括第一和第二泵电路，其中每个泵电路耦合到双泵输入和相应的一个传输栅晶体管的控制端。 每个泵电路通过维持VGS-VT恒定而使其对应的传输门晶体管的操作线性化。 双泵电路用于包括至少一个双泵采样电路，至少一个采样电容器和用于控制输入信号采样定时的控制电路的跟踪和保持电路。 每个双泵采样电路包括传输门和双电荷泵。

公开(公告)号：US06628216B2

公开(公告)日：2003-09-30

申请号：US10207340

申请日：2002-07-29

申请人： Hsin-Shu Chen ,  Kantilal Bacrania ,  Eric C. Sung ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

发明人： Hsin-Shu Chen ,  Kantilal Bacrania ,  Eric C. Sung ,  J. Mikko Hakkarainen ,  Bang-Sup Song ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M110

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

摘要翻译： 一种用于电阻梯的校准系统和方法，其采用电阻对之间的相对测量和调整。 该系统包括耦合到电阻梯的互补对可编程电阻器的电阻树，测量电路，其测量互补对可编程电阻器和控制逻辑之间的电压差。 控制逻辑控制测量电路来测量每对互补的可编程电阻之间的电压差，并调整每对互补可编程电阻对的相对电阻以均衡电压。 通过将测量的电压差转换为比特流的Σ-ΔADC便于测量。 可编程电阻通过二进制加权电阻实现，每次一个LSB​​数字调节。 可以采用较低和较高的调整阈值，以避免不必要的过度调整，同时保持必要的精度水平。

公开(公告)号：US06570523B1

公开(公告)日：2003-05-27

申请号：US10097677

申请日：2002-03-13

申请人： Kantilal Bacrania ,  Hsin-Shu Chen ,  Eric C. Sung ,  Bang-Sup Song ,  J. Mikko Hakkarainen ,  Brian L. Allen ,  Mario Sanchez

发明人： Kantilal Bacrania ,  Hsin-Shu Chen ,  Eric C. Sung ,  Bang-Sup Song ,  J. Mikko Hakkarainen ,  Brian L. Allen ,  Mario Sanchez

IPC分类号： H03M112

CPC分类号： H03M1/165 ,  H03M1/365

摘要： A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

摘要翻译： 一种多级ADC，用于对所选择的子范围进行放大和内插，以将模拟信号转换为数字值流。 ADC对模拟信号进行采样，并提供一个采样信号流。 第一级闪存将每个采样信号转换为第一多位值，并将根据第一多位值的参考梯形图子化为选定的参考信号。 每个附加的次级放大来自前一级的所选择的子信号，闪存转换放大的残留信号以提供附加的多位值，内插每组放大的残留信号，并根据相应的多位值对内插信号进行子范围调整。 最后一级放大并进行闪存转换，以确定最终的多位值。 误差校正器将每组多个位值组合成一个数字值。

公开(公告)号：US5600269A

公开(公告)日：1997-02-04

申请号：US352830

申请日：1994-12-02

申请人： Won-Chul Song ,  Chang-Jun Oh ,  Jong-Ryul Lee ,  Hae-Wook Choi ,  Bang-Sup Song

发明人： Won-Chul Song ,  Chang-Jun Oh ,  Jong-Ryul Lee ,  Hae-Wook Choi ,  Bang-Sup Song

IPC分类号： G11C11/409 ,  G11C7/06 ,  H03F3/45 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03M1/34 ,  G11C7/00

CPC分类号： H03K3/356156 ,  G11C7/062 ,  H03F3/45076 ,  H03K3/356139 ,  H03K3/356191 ,  H03K5/2481 ,  H03K5/249

摘要： Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only while the circuit is at the latch operation. Since a current-consumption is at a zero-state during the normal operation of the comparator circuit, the comparator circuit has a low power-consumption characteristic.

摘要翻译： 公开了一种低功耗型比较器电路，具有用于接收两个输入信号的两个输入端，其中一个输入信号是输入参考信号，另一个是输入比较信号，两个输出端包括信号转换部分 用于将输入信号分别转换为电流信号; 切换部分，用于响应于指示电路的锁存操作或正常操作的锁存信号，控制电流信号传输到电路的输出端; 高电平保持部分，用于仅当不执行电路的锁存操作时，将输出端子的每个电压电平维持为逻辑高电平状态; 放大/确定部分，用于放大当前信号并确定输入比较信号的逻辑电平; 以及输出反馈部分，用于接收输出端子的输出信号，并且仅在电路处于锁存操作时才能使电流在电路中流动到零状态。 由于在比较器电路的正常工作期间电流消耗处于零状态，因此比较器电路具有低功耗特性。