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公开(公告)号:US08133797B2
公开(公告)日:2012-03-13
申请号:US12122614
申请日:2008-05-16
IPC分类号: H01L21/76
CPC分类号: H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/76801
摘要: In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).
摘要翻译: 可以填充高纵横比(通常至少6:1,例如7:1或更高),窄宽度(通常为0.13微米,例如0.1微米或更小)的间隙的原位半导体工艺,而不损坏底层特征和少量 或者不提供空隙或弱点的发生。 沉积保护层以保护具有较低特征密度的衬底区域中的底层特征,使得可以从具有较高特征密度的衬底的区域去除不需要的材料。 该保护层可以在低密度特征上比在高密度特征上沉积更厚,并且可以使用PECVD工艺或低溅射/沉积比HDP CVD工艺沉积。 该保护层也可以是耐氟蚀刻的金属氧化物层,例如氧化锆(ZrO 2)或氧化铝(Al 2 O 3)。
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公开(公告)号:US20090286381A1
公开(公告)日:2009-11-19
申请号:US12122614
申请日:2008-05-16
IPC分类号: H01L21/762
CPC分类号: H01L21/76224 , C23C16/045 , C23C16/401 , H01L21/76801
摘要: In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).
摘要翻译: 可以填充高纵横比(通常至少6:1,例如7:1或更高),窄宽度(通常为0.13微米,例如0.1微米或更小)的间隙的原位半导体工艺,而不损坏底层特征和少量 或者不提供空隙或弱点的发生。 沉积保护层以保护具有较低特征密度的衬底区域中的底层特征,使得可以从具有较高特征密度的衬底的区域去除不需要的材料。 该保护层可以在低密度特征上比在高密度特征上沉积更厚,并且可以使用PECVD工艺或低溅射/沉积比HDP CVD工艺沉积。 该保护层也可以是耐氟蚀刻的金属氧化物层,例如氧化锆(ZrO 2)或氧化铝(Al 2 O 3)。
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公开(公告)号:US08058179B1
公开(公告)日:2011-11-15
申请号:US12343102
申请日:2008-12-23
申请人: Nerissa Draeger , Harald te Nijenhuis , Henner Meinhold , Bart van Schravendijk , Lakshmi Nittala
发明人: Nerissa Draeger , Harald te Nijenhuis , Henner Meinhold , Bart van Schravendijk , Lakshmi Nittala
IPC分类号: H01L21/302
CPC分类号: H01L21/31116 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02337 , H01L21/76837
摘要: Higher overall etch rate and throughput for atomic layer removal (ALR) is achieved. The reaction is a self-limiting process, thus limiting the total amount of material that may be etched per cycle. By pumping down the process station between reacting operations, the reaction is partially “reset.” A higher overall etch rate is achieved by a multiple exposure with pump down ALR process.
摘要翻译: 实现更高的总体蚀刻速率和原子层去除(ALR)的吞吐量。 反应是一种自限制过程,因此限制了每个循环可蚀刻的材料的总量。 通过在反应操作之间泵送工艺站,反应部分地“重新设置”。通过多次曝光通过泵浦ALR工艺实现更高的总体蚀刻速率。
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公开(公告)号:US07981763B1
公开(公告)日:2011-07-19
申请号:US12341943
申请日:2008-12-22
IPC分类号: H01L21/76
CPC分类号: H01L21/76837 , H01L21/02274 , H01L21/31116 , H01L21/76224
摘要: Methods of filling high aspect ratio, narrow width (e.g., sub-50 nm) gaps on a substrate are provided. The methods provide gap fill with little or no incidence of voids, seams or weak spots. According to various embodiments, the methods depositing dielectric material in the gaps to partially fill the gaps, then performing multi-step atomic layer removal process to selectively etch unwanted material deposited on the sidewalls of the gaps. The multi-step atomic layer removal process involves a performing one or more initial atomic layer removal operations to remove unwanted material deposited at the top of the gap, followed by one or more subsequent atomic layer removal operations to remove unwanted material deposited on the sidewalls of the gap. Each atomic layer removal operation involves selectively chemically reacting a portion of the fill material with one or more reactants to form a solid reaction product, which is then removed.
摘要翻译: 提供填充高纵横比,衬底上的窄宽度(例如,小于50nm)间隙的方法。 这些方法提供空隙填充,空隙,接缝或弱点几乎没有或没有发生。 根据各种实施例,在间隙中沉积介电材料以部分地填充间隙的方法,然后执行多步骤原子层去除工艺以选择性地蚀刻沉积在间隙的侧壁上的不需要的材料。 多步骤原子层去除过程涉及执行一个或多个初始原子层去除操作以去除在间隙的顶部沉积的不需要的材料,随后进行一个或多个后续的原子层去除操作以去除沉积在侧壁上的不需要的材料 差距。 每个原子层去除操作涉及使填充材料的一部分与一种或多种反应物选择性地化学反应以形成固体反应产物,然后将其去除。
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公开(公告)号:US09719169B2
公开(公告)日:2017-08-01
申请号:US13329078
申请日:2011-12-16
申请人: Jonathan D. Mohn , Harald te Nijenhuis , Shawn M. Hamilton , Kevin Madrigal , Ramkishan Rao Lingampalli
发明人: Jonathan D. Mohn , Harald te Nijenhuis , Shawn M. Hamilton , Kevin Madrigal , Ramkishan Rao Lingampalli
IPC分类号: H01L21/687 , H01L21/67 , C23C16/458 , C23C16/40 , C23C16/455 , C23C16/46
CPC分类号: C23C16/401 , C23C16/45565 , C23C16/45574 , C23C16/4585 , C23C16/4586 , C23C16/463 , H01L21/67109 , H01L21/6719 , H01L21/68785 , H01L21/68792 , Y10T279/34
摘要: Electronic device fabrication processes, apparatuses and systems for flowable gap fill or flowable deposition techniques are described. In some implementations, a semiconductor fabrication chamber is described which is configured to maintain a semiconductor wafer at a temperature near 0° C. while maintaining most other components within the fabrication chamber at temperatures on the order of 5-10° C. or higher than the wafer temperature.
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公开(公告)号:US09121097B2
公开(公告)日:2015-09-01
申请号:US13631364
申请日:2012-09-28
申请人: Jonathan D. Mohn , Shawn M. Hamilton , Harald te Nijenhuis , Jeffrey E. Lorelli , Kevin Madrigal
发明人: Jonathan D. Mohn , Shawn M. Hamilton , Harald te Nijenhuis , Jeffrey E. Lorelli , Kevin Madrigal
IPC分类号: B05B5/00 , C23C16/455 , H01J37/32
CPC分类号: H01J37/32633 , C23C16/45565 , C23C16/45589 , H01J37/3244
摘要: Apparatuses and techniques for providing for variable radial flow conductance within a semiconductor processing showerhead are provided. In some cases, the radial flow conductance may be varied dynamically during use. In some cases, the radial flow conductance may be fixed but may vary as a function of radial distance from the showerhead centerline. Both single plenum and dual plenum showerheads are discussed.
摘要翻译: 提供了用于在半导体处理花洒内提供可变径向流动电导的装置和技术。 在某些情况下,径向流动电导在使用过程中可能会动态变化。 在一些情况下,径向流动电导可以是固定的,但是可以随着与喷头中心线的径向距离的函数而变化。 讨论了单室和双室淋浴喷头。
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公开(公告)号:US20140061324A1
公开(公告)日:2014-03-06
申请号:US13631364
申请日:2012-09-28
申请人: Jonathan D. Mohn , Shawn M. Hamilton , Harald te Nijenhuis , Jeffrey E. Lorelli , Kevin Madrigal
发明人: Jonathan D. Mohn , Shawn M. Hamilton , Harald te Nijenhuis , Jeffrey E. Lorelli , Kevin Madrigal
IPC分类号: B05B1/14
CPC分类号: H01J37/32633 , C23C16/45565 , C23C16/45589 , H01J37/3244
摘要: Apparatuses and techniques for providing for variable radial flow conductance within a semiconductor processing showerhead are provided. In some cases, the radial flow conductance may be varied dynamically during use. In some cases, the radial flow conductance may be fixed but may vary as a function of radial distance from the showerhead centerline. Both single plenum and dual plenum showerheads are discussed.
摘要翻译: 提供了用于在半导体处理花洒内提供可变径向流动电导的装置和技术。 在某些情况下,径向流动电导在使用过程中可能会动态变化。 在一些情况下,径向流动电导可以是固定的,但是可以随着与喷头中心线的径向距离的函数而变化。 讨论了单室和双室淋浴喷头。
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8.
公开(公告)号:US20120161405A1
公开(公告)日:2012-06-28
申请号:US13329078
申请日:2011-12-16
申请人: Jonathan D. Mohn , Harald te Nijenhuis , Shawn M. Hamilton , Kevin Madrigal , Ramkishan Rao Lingampalli
发明人: Jonathan D. Mohn , Harald te Nijenhuis , Shawn M. Hamilton , Kevin Madrigal , Ramkishan Rao Lingampalli
IPC分类号: B23B31/02
CPC分类号: C23C16/401 , C23C16/45565 , C23C16/45574 , C23C16/4585 , C23C16/4586 , C23C16/463 , H01L21/67109 , H01L21/6719 , H01L21/68785 , H01L21/68792 , Y10T279/34
摘要: Electronic device fabrication processes, apparatuses and systems for flowable gap fill or flowable deposition techniques are described. In some implementations, a semiconductor fabrication chamber is described which is configured to maintain a semiconductor wafer at a temperature near 0° C. while maintaining most other components within the fabrication chamber at temperatures on the order of 5-10° C. or higher than the wafer temperature.
摘要翻译: 描述了用于可流动间隙填充或可流动沉积技术的电子器件制造工艺,设备和系统。 在一些实施方案中,描述了半导体制造室,其被配置为将半导体晶片维持在接近0℃的温度,同时将制造室内的大多数其它组分保持在5-10℃或更高的温度 晶圆温度。
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