公开(公告)号：US6165906A

公开(公告)日：2000-12-26

申请号：US237412

申请日：1999-01-26

申请人： Basab Bandyopadhyay ,  Douglas J. Bonser ,  Michael J. McBride

发明人： Basab Bandyopadhyay ,  Douglas J. Bonser ,  Michael J. McBride

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76235 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31662 ,  H01L21/32

摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate involves oxidizing unmasked portions of a semiconductor substrate prior to etching an isolation trench into the semiconductor substrate. By oxidizing the unmasked portions of the semiconductor prior to etching, an isolation trench with rounded corners may be formed.

摘要翻译： 在半导体衬底内的有源区域之间形成改进的隔离沟槽的方法包括在将隔离沟槽蚀刻到半导体衬底之前氧化半导体衬底的未屏蔽部分。 通过在蚀刻之前氧化半导体的未屏蔽部分，可以形成具有圆角的隔离沟槽。

公开(公告)号：US06309947B1

公开(公告)日：2001-10-30

申请号：US08944314

申请日：1997-10-06

申请人： Basab Bandyopadhyay ,  Douglas J. Bonser

发明人： Basab Bandyopadhyay ,  Douglas J. Bonser

IPC分类号： H01L21762

CPC分类号： H01L21/76224

摘要： A method of making a semiconductor device with improved isolation region to active region topography includes forming a masking layer on a surface of a substrate. A portion of the masking layer is removed to define one or more field regions and at least one trench is formed in the one or more field regions. An oxide layer is formed which substantially fills the trench and then a portion of the oxide layer is removed to leave the oxide layer with a relatively planar surface that is recessed with respect to the masking layer. The masking layer is then removed to expose the substrate. There may be a height differential between the substrate surface and the relatively planer surface of the oxide layer, however, the height differential is substantially less than the thickness of the masking layer.

摘要翻译： 制造具有改善的隔离区域到有源区域形貌的半导体器件的方法包括在衬底的表面上形成掩模层。 去除掩模层的一部分以限定一个或多个场区域，并且在一个或多个场区域中形成至少一个沟槽。 形成氧化物层，其基本上填充沟槽，然后去除氧化物层的一部分以使氧化物层具有相对于掩模层凹陷的相对平坦的表面。 然后去除掩模层以露出衬底。 在衬底表面和氧化物层的相对平坦的表面之间可能存在高度差，然而，高差大大小于掩模层的厚度。

公开(公告)号：US06376330B1

公开(公告)日：2002-04-23

申请号：US08655242

申请日：1996-06-05

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L2176

CPC分类号： H01L21/7682

摘要： A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.

摘要翻译： 提供一种电介质材料，其具有在电介质中有目的地形成的气隙。 电介质被沉积，并且在相应的互连线之间形成气隙。 有意地控制互连线之间的几何形状以实现在电介质CVD期间产生气隙所需的大的纵横比。 互连之间存在空隙，以减少线间电容，从而减少与紧密间隔的互连相关的传播延迟。

公开(公告)号：US6127719A

公开(公告)日：2000-10-03

申请号：US038464

申请日：1998-03-11

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/74 ,  H01L29/00 ,  H01L31/119

CPC分类号： H01L21/74

摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

摘要翻译： 提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。 在形成场电介质之后，将子场导电层置于硅衬底内。 导电层表示驻留在隔离器件之间的掩埋互连。 然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。 埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

公开(公告)号：US06074927A

公开(公告)日：2000-06-13

申请号：US87662

申请日：1998-06-01

申请人： Nick Kepler ,  Basab Bandyopadhyay ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Nick Kepler ,  Basab Bandyopadhyay ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop over the pad oxide layer is removed by anisotropic etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. The portion of the polish stop remaining in the trench and on the oxide liner at the trench edges serves as a protective spacer, protecting the field oxide from erosion during subsequent processing steps.

摘要翻译： 形成浅沟槽隔离结构，其使得能够在沟槽边缘处生长高质量的栅极氧化物，并且保护场氧化物在后栅极处理（例如在局部互连蚀刻期间）中的气蚀，从而允许形成高质量 植入路口。 实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。 在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面中生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上的沟槽中。 然后将抛光停止层掩蔽到沟槽边缘，并且沟槽中的抛光停止点被各向异性地蚀刻，以去除沟槽底部的抛光停止部，留下覆盖氧化物衬垫上的沟槽的侧表面和边缘的部分 。 然后用绝缘材料填充沟槽，使绝缘材料平坦化，并通过各向异性蚀刻去除衬垫氧化物层上的抛光剂停止。 因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。 保留在沟槽中的抛光停止部分和在沟槽边缘处的氧化物衬垫上的部分用作保护间隔物，在随后的处理步骤期间保护场氧化物免受侵蚀。

公开(公告)号：US5968843A

公开(公告)日：1999-10-19

申请号：US768278

申请日：1996-12-18

申请人： Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/3105 ,  H01L21/302

CPC分类号： H01L21/31053

摘要： An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.

摘要翻译： 一种用于平坦化层间电介质的改进方法，包括两个化学机械抛光步骤。 在形成包含一对形貌峰之间的形貌谷的层间电介质之后，使用具有第一刚性的第一抛光垫在第一抛光步骤中以第一力进行化学机械抛光的电介质以使尖锐的电介质拐角或边缘 存在于峰谷之间的过渡处。 在第一抛光步骤使边缘变圆之后，用第二刚性的第二抛光垫进行第二抛光步骤。 第二抛光垫比第一抛光垫更刚性，第二抛光垫大于第一抛光垫。 第二抛光步骤使用高粘度浆料来减少靠近电介质谷的区域中的浆料周转，从而减少了谷中的化学蚀刻并提高了平坦化效率。

公开(公告)号：US5783864A

公开(公告)日：1998-07-21

申请号：US655248

申请日：1996-06-05

申请人： Robert Dawson ,  Mark W. Michael ,  William S. Brennan ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause

发明人： Robert Dawson ,  Mark W. Michael ,  William S. Brennan ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/41

CPC分类号： H01L23/5226 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5222 ,  H01L2924/0002

摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

公开(公告)号：US5767000A

公开(公告)日：1998-06-16

申请号：US655243

申请日：1996-06-05

申请人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

发明人： H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/74 ,  H01L21/76

CPC分类号： H01L21/74

摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

摘要翻译： 提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。 在形成场电介质之后，将子场导电层置于硅衬底内。 导电层表示驻留在隔离器件之间的掩埋互连。 然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。 埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

公开(公告)号：US06380047B1

公开(公告)日：2002-04-30

申请号：US09634990

申请日：2000-08-08

申请人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

摘要翻译： 使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料 沟渠 然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。 由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。 此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

公开(公告)号：US6124183A

公开(公告)日：2000-09-26

申请号：US992490

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分 绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。 由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。