公开(公告)号：US20070195591A1

公开(公告)日：2007-08-23

申请号：US11790444

申请日：2007-04-25

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

摘要翻译： 半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧 第一面相反 该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接 。 该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

公开(公告)号：US20060285380A1

公开(公告)日：2006-12-21

申请号：US11315130

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.

摘要翻译： 相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。 多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。 多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

公开(公告)号：US07460386B2

公开(公告)日：2008-12-02

申请号：US11790444

申请日：2007-04-25

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

摘要翻译： 半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧 第一面相反 该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接 。 该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

公开(公告)号：US07227776B2

公开(公告)日：2007-06-05

申请号：US11315130

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.

摘要翻译： 相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。 多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。 多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

公开(公告)号：US07397681B2

公开(公告)日：2008-07-08

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C27/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US07349246B2

公开(公告)日：2008-03-25

申请号：US11483477

申请日：2006-07-10

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C8/04 ,  G11C8/10 ,  G11C8/12 ,  G11C8/08 ,  G11C7/20 ,  G11C8/18

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.

摘要翻译： 在相变存储器件的触发方法和能够有效地执行点火操作的相变存储器中，相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动 单元。 每个存储单元阵列块具有相变存储单元。 计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。 解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字 行地址，其使能所选存储单元阵列块的冗余字线。 驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。 根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。 此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

公开(公告)号：US20060250885A1

公开(公告)日：2006-11-09

申请号：US11483477

申请日：2006-07-10

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-Keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C8/00

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.

摘要翻译： 描述能够有效地执行点火操作的相变存储器件和相变存储器的点火方法。 相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。 每个存储单元阵列块具有相变存储单元。 计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。 解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字 行地址，其使能所选存储单元阵列块的冗余字线。 驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。 根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。 此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

公开(公告)号：US20060215440A1

公开(公告)日：2006-09-28

申请号：US11348432

申请日：2006-02-06

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C13/0004

摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

公开(公告)号：US20050052904A1

公开(公告)日：2005-03-10

申请号：US10929511

申请日：2004-08-30

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

IPC分类号： G11C13/02 ,  G11C11/00 ,  G11C16/20

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.

摘要翻译： 描述能够有效地执行点火操作的相变存储器件和相变存储器的点火方法。 相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动单元。 每个存储单元阵列块具有相变存储单元。 计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。 解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字 行地址，其使能所选存储单元阵列块的冗余字线。 驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。 根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。 此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。

公开(公告)号：US07254055B2

公开(公告)日：2007-08-07

申请号：US10929511

申请日：2004-08-30

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C29/00 ,  G11C8/12 ,  G11C8/04

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block. The driving unit applies a firing current to the memory cell array blocks in response to the firing mode signal. According to the phase change memory device and the initial firing method, the time taken to perform the initial firing operation can be reduced. In addition, since the numbers of the needed signals are minimized, a large number of chips on a single wafer can be simultaneously tested.

摘要翻译： 在相变存储器件的触发方法和能够有效地执行点火操作的相变存储器中，相变存储器件包括多个存储单元阵列块，计数器时钟生成单元，解码单元和驱动 单元。 每个存储单元阵列块具有相变存储单元。 计数器时钟产生单元响应于外部时钟信号和触发模式信号输出第一至第三计数器时钟信号，其中第一至第三计数器时钟信号具有不同的周期。 解码单元响应于第一至第三计数器时钟信号输出选择多个存储单元阵列块中的一个的块地址，使得能够选择的存储单元阵列块的字线的字线地址和冗余字 行地址，其使能所选存储单元阵列块的冗余字线。 驱动单元响应于点火模式信号向存储单元阵列块施加点火电流。 根据相变存储器件和初始烧制方法，可以减少执行初始点火操作所花费的时间。 此外，由于所需信号的数量最小化，可以同时测试单个晶片上的大量芯片。