公开(公告)号：US20070195591A1

公开(公告)日：2007-08-23

申请号：US11790444

申请日：2007-04-25

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

摘要翻译： 半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧 第一面相反 该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接 。 该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

公开(公告)号：US20060285380A1

公开(公告)日：2006-12-21

申请号：US11315130

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.

摘要翻译： 相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。 多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。 多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

公开(公告)号：US07460386B2

公开(公告)日：2008-12-02

申请号：US11790444

申请日：2007-04-25

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/00

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： The layout method for a semiconductor device includes locating a plurality of first bit line selection circuits at a first side of a variable resistive memory cell block, and locating a plurality of second bit line selection circuits at a second side of the variable resistive memory cell block opposite the first side. The method further includes connecting the first bit line selection circuits with respective odd-numbered local bit lines of the variable resistive memory cell block, and connecting the second bit line selection circuits with respective even-numbered local bit lines of the variable resistive memory cell block. The method still further includes selectively connecting respective odd-numbered local bit lines to a global bit line using the first bit line selection circuits, and selectively connecting respective even-numbered local bit lines to the global bit line using the second bit line selection circuits.

摘要翻译： 半导体器件的布局方法包括在可变电阻存储器单元块的第一侧定位多个第一位线选择电路，并且将多个第二位线选择电路定位在可变电阻存储器单元块的第二侧 第一面相反 该方法还包括将第一位线选择电路与可变电阻存储单元块的相应奇数本地位线连接，并将第二位线选择电路与可变电阻存储单元块的各个偶数本地位线连接 。 该方法还包括使用第一位线选择电路选择性地将相应的奇数本地位线连接到全局位线，并且使用第二位线选择电路选择性地将各偶数本地位线连接到全局位线。

公开(公告)号：US07227776B2

公开(公告)日：2007-06-05

申请号：US11315130

申请日：2005-12-23

申请人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

发明人： Beak-hyung Cho ,  Du-eung Kim ,  Byung-gil Choi ,  Choong-keun Kwak

IPC分类号： G11C11/00 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C13/0004

摘要： A phase change memory device includes a phase change memory cell block having alternating odd-numbered and even-numbered local bit lines, a global bit line, a plurality of first bit line selection circuits, and a plurality of second bit line selection circuits. The plurality of first bit line selection circuits are located at a first side of the phase change memory cell block and selectively connect respective odd-numbered local bit lines to the global bit line. The plurality of second bit line selection circuits are located at second side of the phase change memory cell block (opposite the first side) and selectively connect respective even-numbered local bit lines to the global bit line.

摘要翻译： 相变存储器件包括具有交替的奇数和偶数编号的局部位线，全局位线，多个第一位线选择电路和多个第二位线选择电路的相变存储器单元块。 多个第一位线选择电路位于相变存储单元块的第一侧，并且选择性地将各自的奇数本地位线连接到全局位线。 多个第二位线选择电路位于相变存储单元块的第二侧（与第一侧相反），并且选择性地将各偶数的局部位线连接到全局位线。

公开(公告)号：US07573766B2

公开(公告)日：2009-08-11

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/00

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US07450415B2

公开(公告)日：2008-11-11

申请号：US11640956

申请日：2006-12-19

申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

IPC分类号： G11C11/00

CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

公开(公告)号：US20080062741A1

公开(公告)日：2008-03-13

申请号：US11898125

申请日：2007-09-10

申请人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

发明人： Byung-gil Choi ,  Beak-hyung Cho ,  Du-eung Kim ,  Chang-han Choi ,  Yu-hwan Ro

IPC分类号： G11C29/44

CPC分类号： G11C13/0004 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

摘要翻译： 提供了一种测试相变随机存取存储器（PRAM）的方法。 该方法可以包括提供多个PRAM单元，每个PRAM单元分别耦合在多个第一线中的每一条与多条第一线相交的多条第二线中的每条之间，同时选择多条第一条线中的至少一条，同时取消选择其余的第一条线， 所述多个第二线路将所选择的所述多个第一线路中的至少一个预充电到预定或给定的电压电平，并且感测所选择的第一线路的电压电平的变化，同时向所选择的第一线路提供监视电压 线。

公开(公告)号：US20070153616A1

公开(公告)日：2007-07-05

申请号：US11640956

申请日：2006-12-19

申请人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

发明人： Du-eung Kim ,  Chang-soo Lee ,  Woo-yeong Cho ,  Beak-hyung Cho ,  Byung-gil Choi

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

摘要： A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.

摘要翻译： 提供了相变存储器件。 相变存储器件包括相变存储器单元阵列，该相变存储单元阵列包括具有连接在多个位线和第一字线中的每一个之间的多个相变存储单元的第一存储器块，具有第 多个相变存储单元，分别连接在多个位线和第二字线之间，第一和第二下拉晶体管下拉第一和第二字线的每个电压电平并共享一个节点;以及 行驱动器，包括第一和第二上拉晶体管，其拉出第一和第二字线的每个电压电平。

公开(公告)号：US07499306B2

公开(公告)日：2009-03-03

申请号：US11772569

申请日：2007-07-02

申请人： Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

发明人： Byung-gil Choi ,  Choong-keun Kwak ,  Sang-beom Kang ,  Joon-yong Choi

IPC分类号： G11C11/00

CPC分类号： G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2211/5647

摘要： Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a set state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

摘要翻译： 提供一种将相变材料的电阻维持在恒定电阻范围内的置换状态的相变存储器件和方法。 在该方法中，将数据提供给第一相变存储器单元，然后首先确定存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据是否相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据不相同，则向第一相变存储单元提供互补写入电流，并且第二相位变换存储单元是否将数据 存储在第一相变存储单元中，提供给第一相变存储单元的数据相同。 如果存储在第一相变存储单元中的数据和提供给第一相变存储单元的数据相同，则将数据提供给第二相变存储单元。

公开(公告)号：US08243495B2

公开(公告)日：2012-08-14

申请号：US12379399

申请日：2009-02-20

申请人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

发明人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C2213/72

摘要： A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.

摘要翻译： 能够降低字线的电阻的相变随机存取存储器（PRAM）装置可以包括半导体存储器件的多个主字线或在与多个 子字线被排列。 半导体存储器件或PRAM还可以包括用于连接多个切割子字线的跳跃触点。 在包括多个主字线和多个子字线在不同层中的PRAM装置中，用于将多个主字线连接到子字线解码器的晶体管的跳转触点的数量是相同的 在每个子字线或多个主字线被多次弯曲，从而可以减少字线上的寄生电阻和功耗，并且可以增加感测裕度。