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公开(公告)号：US20080084922A1
公开(公告)日：2008-04-10
申请号：US11543508
申请日：2006-10-05
摘要： Multiprotocol multiplex wireless communication apparatus and methods are described. These apparatus and methods are capable of simultaneously communicating with multiple wireless environments in accordance with different wireless communications protocols. In particular, these apparatus and methods are capable of transmitting and receiving multiplex signals that include constituent data-carrying signals that conform to different wireless communications protocols.
摘要翻译： 描述了多协议多路复用无线通信装置和方法。 这些装置和方法能够根据不同的无线通信协议同时与多个无线环境进行通信。 特别地，这些装置和方法能够发送和接收包括符合不同无线通信协议的组成数据携带信号的多路复用信号。
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公开(公告)号：US20080084919A1
公开(公告)日：2008-04-10
申请号：US11606448
申请日：2006-11-30
IPC分类号： H04B1/00
摘要： In a wireless transmission method, an input data signal corresponding to a serial combination of a first transmit data signal and a second transmit data signal is received. The first and second transmit data signals are phase-modulated with different first and second spreading code signals to produce first and second DSSS transmit signals, which are serially output as a baseband transmit signal that is up-converted to a selected wireless transmission frequency range. The first and second phase-modulated signals are serially output as a baseband transmit signal. In a wireless reception method, an input receive signal is down-converted to a baseband receive signal corresponding to a serial combination of first and second time-interleaved DSSS receive signals in a baseband frequency range. The first and second DSSS receive signals are phase-demodulated with different first and second de-spreading code signals to produce first and second receive data signals.
摘要翻译： 在无线发送方法中，接收对应于第一发送数据信号和第二发送数据信号的串行组合的输入数据信号。 第一和第二发射数据信号用不同的第一和第二扩展码信号进行相位调制，以产生第一和第二DSSS发射信号，其被串行地输出为上变频到所选无线传输频率范围的基带发射信号。 串行输出第一和第二相位调制信号作为基带发送信号。 在无线接收方法中，将输入接收信号下变频为与基带频率范围内的第一和第二时间交织的DSSS接收信号的串行组合相对应的基带接收信号。 第一和第二DSSS接收信号用不同的第一和第二去扩展码信号进行相位解调，以产生第一和第二接收数据信号。
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公开(公告)号：US08219778B2
公开(公告)日：2012-07-10
申请号：US12037940
申请日：2008-02-27
CPC分类号： G06F13/28
摘要： The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.
摘要翻译： 这里描述的实施例提供对可能分散在存储器中的一组缓冲器的个体数据存储位置的随机访问。 这些实施例提供一种虚拟存储器接口，其将平坦存储器线性寻址空间中的虚拟地址作为根据该组缓冲器排列成序列的物理存储器地址的索引。 以这种方式，这些实施例使得设备（例如，处理器）能够直接且顺序地访问分段数据项（例如分组）的所有分散物理存储器位置，而不必执行任何存储器分段或寻呼过程。 在一些实施例中，这些访问包括对分散数据存储位置的读取和写入访问。
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公开(公告)号：US20090216964A1
公开(公告)日：2009-08-27
申请号：US12037940
申请日：2008-02-27
CPC分类号： G06F13/28
摘要： The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.
摘要翻译： 这里描述的实施例提供对可能分散在存储器中的一组缓冲器的个体数据存储位置的随机访问。 这些实施例提供一种虚拟存储器接口，其将平坦存储器线性寻址空间中的虚拟地址作为根据该组缓冲器排列成序列的物理存储器地址的索引。 以这种方式，这些实施例使得设备（例如，处理器）能够直接且顺序地访问分段数据项（例如分组）的所有分散物理存储器位置，而不必执行任何存储器分段或寻呼过程。 在一些实施例中，这些访问包括对分散数据存储位置的读取和写入访问。
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公开(公告)号：US20070115160A1
公开(公告)日：2007-05-24
申请号：US11600945
申请日：2006-11-16
申请人： Bendik Kleveland , Junfeng Xu , Thomas Lee , Dickson Wong
发明人： Bendik Kleveland , Junfeng Xu , Thomas Lee , Dickson Wong
IPC分类号： H03M1/66
CPC分类号： H04L27/2331
摘要： Apparatus and methods of differentially decoding analog baseband signals are described. In one aspect, a wireless communication apparatus includes a baseband filtering stage and a differential decoder stage. The baseband filtering stage receives a DPSK analog baseband signal differentially encoded with phase shift differences in successive symbol periods. The baseband filtering stage selectively passes frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal. The differential decoder includes a delay circuit and a combiner circuit. The delay circuit produces from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period. The combiner circuit combines values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.
摘要翻译： 描述差分解码模拟基带信号的装置和方法。 一方面，无线通信装置包括基带滤波级和差分解码级。 基带滤波级接收在连续符号周期中以相移差差编码的DPSK模拟基带信号。 基带滤波级选择性地通过通带频带范围内的DPSK模拟基带信号中的频率，以产生经滤波的模拟信号。 差分解码器包括延迟电路和组合器电路。 延迟电路从经滤波的模拟信号产生参考信号，该参考信号在一个符号周期内保持滤波后的模拟信号的特征值。 组合器电路将当前符号周期期间滤波的模拟信号的特征值与参考信号的值组合，以产生表示DPSK模拟基带信号的差分解码的结果信号。
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公开(公告)号：US07759916B2
公开(公告)日：2010-07-20
申请号：US12118773
申请日：2008-05-12
申请人： Bendik Kleveland
发明人： Bendik Kleveland
CPC分类号： G05F1/563 , H02M3/1584 , H02M2001/0032 , H02M2001/0045 , Y02B70/16
摘要： A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.
摘要翻译： 提供了一种电压调节器装置和相关方法，用于向电子设备提供有效的电压调节。 高效调节器400从节点VIN处的电池或其他电源接收VIN上的输入电压，并在节点VOUT向负载装置404提供稳定的调节电压。 负载装置404拉动不同数量的电流，并且根据其工作条件对VOUT上的电压需要不同程度的容差。 数据收集和控制电路401能够启用和禁用调节器402和调节器403.数据收集和控制电路401还能够测量与负载设备404相关联的某些性能参数和负载设备404的操作条件。数据收集和控制 如果所述操作条件使得当数据收集和控制电路401启用调节器403时，与加载404相关联的性能参数低于预定标准，则电路401使得调节器402能够启用调节器402。
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公开(公告)号：US07564707B2
公开(公告)日：2009-07-21
申请号：US11843404
申请日：2007-08-22
申请人： Bendik Kleveland
发明人： Bendik Kleveland
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L27/101 , H01L27/112 , H01L27/1122
摘要： An apparatus includes a semiconductor substrate, elongated diffused well regions, and elongated conductors. The semiconductor substrate has a first electrical conductivity type. The elongated diffused well regions are in the semiconductor substrate. The diffused well regions have a second electrical conductivity type opposite the first electrical conductivity type. Each of the elongated electrical conductors crosses the diffused well regions at respective locations of one-time programmable memory cells. Each of the memory cells includes a antifuse structure between the respective diffused well region and the respective electrical conductor. Each of the memory cells has a first state in which the antifuse structure has a first electrical resistance and a second state in which the antifuse structure has a second electrical resistance lower than the first electrical resistance. In the second state, each of the memory cells includes a rectifying junction between the respective diffused well region and the respective electrical conductor.
摘要翻译： 一种装置包括半导体衬底，细长扩散阱区和细长导体。 半导体衬底具有第一导电类型。 细长扩散阱区位于半导体衬底中。 扩散阱区具有与第一导电类型相反的第二导电类型。 每个细长电导体在一次可编程存储器单元的相应位置处与扩散阱区域交叉。 每个存储单元包括在各个扩散阱区域和相应的电导体之间的反熔丝结构。 每个存储单元具有其中反熔丝结构具有第一电阻的第一状态和其中反熔丝结构具有低于第一电阻的第二电阻的第二状态。 在第二状态下，每个存储单元包括各个扩散阱区和相应电导体之间的整流结。
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公开(公告)号：US20080278247A1
公开(公告)日：2008-11-13
申请号：US12171277
申请日：2008-07-10
申请人： Stanley Wang , Bendik Kleveland , Thomas H. Lee
发明人： Stanley Wang , Bendik Kleveland , Thomas H. Lee
IPC分类号： H03B1/04
CPC分类号： H03L7/099
摘要： A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).
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公开(公告)号：US20060291303A1
公开(公告)日：2006-12-28
申请号：US11158396
申请日：2005-06-22
申请人： Bendik Kleveland , Tae Lee , Seung Yu , Chia Yang , Feng Li , Xiaoyu Yang
发明人： Bendik Kleveland , Tae Lee , Seung Yu , Chia Yang , Feng Li , Xiaoyu Yang
IPC分类号： G11C29/00
CPC分类号： G11C29/816 , G11C17/14
摘要： A method and apparatus for programming a memory array are disclosed. In one embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, the word line is repaired with a redundant word line. The word lines are then reprogrammed and rechecked for defects. In another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line. If a defect is detected, that word line is repaired along with a previously-programmed adjacent word line. In yet another embodiment, after each word line is programmed, an attempt is made to detect a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired with redundant word lines.
摘要翻译： 公开了一种用于对存储器阵列进行编程的方法和装置。 在一个实施例中，在每个字线被编程之后，尝试检测该字线上的缺陷。 如果检测到缺陷，则用冗余字线修复字线。 字线然后被重新编程并重新检查缺陷。 在另一个实施例中，在每个字线被编程之后，尝试检测该字线上的缺陷。 如果检测到缺陷，则该字线与预先编程的相邻字线一起被修复。 在另一个实施例中，在每个字线被编程之后，尝试检测该字线上的缺陷和预先编程的相邻字线。 如果在该字线上检测到缺陷，则该字线和先前编程的相邻字线用冗余字线修复。
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10.发明授权公开(公告)号：US06816410B2
公开(公告)日：2004-11-09
申请号：US10809146
申请日：2004-03-25
IPC分类号： G11C1604
CPC分类号： B82Y10/00 , G11C5/025 , G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0014 , G11C13/0028 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2207/063 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021
摘要： A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
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