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    System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
    1.
    发明授权
    System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers 失效
    用于通过启用多个预驱动器和多个输出驱动器来调节驱动电路的输出上的转换速率的系统

    公开(公告)号：US6047346A

    公开(公告)日：2000-04-04

    申请号：US17529

    申请日：1998-02-02

    申请人： Benedict C. Lau ,  Jason Wei ,  Tsyr-Chyang Ho ,  Samir A. Patel ,  Yiu-Fai Chan

    发明人： Benedict C. Lau ,  Jason Wei ,  Tsyr-Chyang Ho ,  Samir A. Patel ,  Yiu-Fai Chan

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4072

    摘要： An interface circuit providing a high speed bus. According to one embodiment, the interface circuitry includes a plurality of I/O pins coupled to a plurality of bus drivers, wherein each bus driver is configured to adjust the rise time, fall time, and drive strength of outputs signal on the I/O pins based on process-voltage-temperature ("PVT") conditions. The circuitry used to adjust the I/O outputs includes a slew rate control circuit, a current control circuit, and a delay lock loop ("DLL").

    摘要翻译： 提供高速总线的接口电路。 根据一个实施例，接口电路包括耦合到多个总线驱动器的多个I / O引脚，其中每个总线驱动器被配置为调整I / O上的输出信号的上升时间，下降时间和驱动强度 基于过程电压 - 温度（“PVT”）条件的引脚。 用于调整I / O输出的电路包括压摆率控制电路，电流控制电路和延迟锁定环（“DLL”）。

    Delay locked loop circuitry for clock delay adjustment
    2.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H04L700

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay-locked loop circuitry for clock delay adjustment
    3.
    发明授权
    Delay-locked loop circuitry for clock delay adjustment 失效
    用于时钟延迟调整的延迟锁定环路

    公开(公告)号：US6125157A

    公开(公告)日：2000-09-26

    申请号：US795657

    申请日：1997-02-06

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/24 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H04L7/0008 ,  H04L7/0025

    摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.

    摘要翻译： 延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay locked loop circuitry for clock delay adjustment
    4.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 失效
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US07039147B2

    公开(公告)日：2006-05-02

    申请号：US10366865

    申请日：2003-02-14

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H03D3/24

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

    Scalable I/O signaling topology using source-calibrated reference voltages
    6.
    发明授权
    Scalable I/O signaling topology using source-calibrated reference voltages 有权

    公开(公告)号：US07133945B2

    公开(公告)日：2006-11-07

    申请号：US10942720

    申请日：2004-09-15

    申请人： Benedict C. Lau

    发明人： Benedict C. Lau

    IPC分类号： G06F13/00 ,  G11C5/14

    CPC分类号： H04L25/028

    摘要： An embodiment of the invention is a scalable I/O interface signaling technology for improved communication between semiconductor devices. In one embodiment, a system contains a first semiconductor device that includes a first characterization mechanism, a control logic coupled to the first characterization mechanism, a voltage generating mechanism coupled to the control logic and a transmit buffer. The control logic adjusts at least a first voltage generated by the voltage generating mechanism based on at least a value determined by the first characterization mechanism. The first voltage is coupled to the transmit buffer to define at least a transmit voltage signal level. In an alternate embodiment, the first voltage is coupled to a receive buffer in a second semiconductor device to define at least a receive voltage signal level.

    Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback
    7.
    发明授权
    Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback 失效
    具有响应于反馈的电压驱动器进行分布式电压补偿的方法和装置

    公开(公告)号：US07046078B2

    公开(公告)日：2006-05-16

    申请号：US11126643

    申请日：2005-05-11

    申请人： Huy M. Nguyen ,  Benedict C. Lau ,  Adam Chuen-Huei Chou ,  Roxanne T. Vu

    发明人： Huy M. Nguyen ,  Benedict C. Lau ,  Adam Chuen-Huei Chou ,  Roxanne T. Vu

    IPC分类号： G05F1/10

    CPC分类号： G06F1/26

    摘要： An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

    摘要翻译： 集成电路具有参考分布式参考电压工作的一个或多个组件。 参考电压驱动器产生补偿的参考电压，并且补偿的参考电压被分配以在组件处形成分布式参考电压。 由于迹线电阻和栅极泄漏等因素，分布式参考电压相对于补偿参考电压降低。 参考电压驱动器响应于从分布式参考电压得到的反馈，以调整补偿的参考电压，使得分布式参考电压近似等于标称参考电压。

    Apparatus and method for generating multiple clock signals from a single loop circuit
    9.
    发明授权
    Apparatus and method for generating multiple clock signals from a single loop circuit 有权
    用于从单回路电路产生多个时钟信号的装置和方法

    公开(公告)号：US06469555B1

    公开(公告)日：2002-10-22

    申请号：US09642484

    申请日：2000-08-18

    申请人： Benedict C. Lau ,  Stefanos Sidiropoulos

    发明人： Benedict C. Lau ,  Stefanos Sidiropoulos

    IPC分类号： H03L706

    CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/0812

    摘要： A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay element is coupled to receive the first clock signal from the delay-locked loop circuit. The second delay element also outputs a second clock signal that is delayed relative to the first clock signal by the first time period. The delay-locked loop circuit may include a phase detector to identify phase differences between the first clock signal and the reference clock signal. A third delay element may be coupled between the delay-locked loop circuit and the second delay element.

    摘要翻译： 延迟锁定环路产生第一时钟信号。 延迟锁定环电路包括耦合在延迟锁定环电路的反馈路径中的第一延迟元件，以相对于参考时钟信号相对于第一时间段推进第一时钟信号。 第二延迟元件被耦合以从延迟锁定环路电路接收第一时钟信号。 第二延迟元件还输出相对于第一时钟信号延迟第一时间段的第二时钟信号。 延迟锁定环路电路可以包括相位检测器，用于识别第一时钟信号和参考时钟信号之间的相位差。 第三延迟元件可以耦合在延迟锁定环路电路和第二延迟元件之间。

    Differential amplifier with selectable hysteresis and buffered filter
    10.
    发明授权
    Differential amplifier with selectable hysteresis and buffered filter 失效
    具有可选迟滞和缓冲滤波器的差分放大器

    公开(公告)号：US06384637B1

    公开(公告)日：2002-05-07

    申请号：US09588437

    申请日：2000-06-06

    申请人： Huy M. Nguyen ,  Benedict C. Lau

    发明人： Huy M. Nguyen ,  Benedict C. Lau

    IPC分类号： G01R1900

    CPC分类号： H03K3/3565

    摘要： A differential amplifier with reduced noise sensitivity enables the bus to operate more efficiently at higher data rates. The amplifier includes an input stage with a pair of adjustable resistive loads that alter the gain of the input stage. A differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive- and negative-going voltage signals.

    摘要翻译： 具有降低噪声灵敏度的差分放大器使总线能够以更高的数据速率更有效地运行。 放大器包括具有改变输入级的增益的一对可调电阻负载的输入级。 差分输出级接收输入级的输出并产生一对互补输出信号。 这些输出信号被反馈到可调​​电阻负载，使得输入级的增益取决于输出信号的电平。 反馈是正的，因此本发明的放大器的电压传递特性对于正负电压信号具有不同的输入阈值。