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    Delay locked loop circuitry for clock delay adjustment
    2.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 失效
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US07039147B2

    公开(公告)日：2006-05-02

    申请号：US10366865

    申请日：2003-02-14

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H03D3/24

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

    Delay locked loop circuitry for clock delay adjustment
    3.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H04L700

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay-locked loop circuitry for clock delay adjustment
    4.
    发明授权
    Delay-locked loop circuitry for clock delay adjustment 失效
    用于时钟延迟调整的延迟锁定环路

    公开(公告)号：US6125157A

    公开(公告)日：2000-09-26

    申请号：US795657

    申请日：1997-02-06

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/24 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H04L7/0008 ,  H04L7/0025

    摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.

    摘要翻译： 延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Circuitry for the delay adjustment of a clock signal
    5.
    发明授权
    Circuitry for the delay adjustment of a clock signal 失效
    电路用于时钟信号的延迟调整

    公开(公告)号：US5945862A

    公开(公告)日：1999-08-31

    申请号：US904203

    申请日：1997-07-31

    申请人： Kevin S. Donnelly ,  Jun Kim ,  Bruno W. Garlepp ,  Mark A. Horowitz ,  Thomas H. Lee ,  Pak Shing Chau ,  Jared L. Zerbe ,  Clemenz L. Portmann ,  Yiu-Fai Chan

    发明人： Kevin S. Donnelly ,  Jun Kim ,  Bruno W. Garlepp ,  Mark A. Horowitz ,  Thomas H. Lee ,  Pak Shing Chau ,  Jared L. Zerbe ,  Clemenz L. Portmann ,  Yiu-Fai Chan

    IPC分类号： H03K5/13 ,  H03H11/26

    CPC分类号： H03K5/1565 ,  H03K5/13

    摘要： Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries. Phase interpolation between the taps of the delay chain is employed to increase the resolution of the adjustment to the periodic signal. Duty cycle correction of the input clock and the selected output clock is employed to improve accuracy.

    摘要翻译： 用于在整个周期信号的整个周期内调整进入周期信号（通常为时钟信号）的相位的电路。 相位调整电路具有高分辨率，并且仅在延迟链中仅使用延伸元件的数量来跨越至少输入信号的周期，或者在双链接收互补时钟的情况下至少半个周期。 相位调整电路包括具有多个抽头的延迟链，边界检测器，用于指示抽头何时处于输入周期性信号的相位边界;以及选择电路，用于基于边界从延迟链中选择一个抽头 检测器输出和选择电路输入，使得所选择的抽头是输入周期性信号的期望的相位调整，并且输入信号的延迟在其相位边界上是可调节的。 使用延迟链的抽头之间的相位插值来增加对周期性信号的调整的分辨率。 采用输入时钟和选择的输出时钟的占空比校正来提高精度。

    System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
    7.
    发明授权
    System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers 失效
    用于通过启用多个预驱动器和多个输出驱动器来调节驱动电路的输出上的转换速率的系统

    公开(公告)号：US6047346A

    公开(公告)日：2000-04-04

    申请号：US17529

    申请日：1998-02-02

    申请人： Benedict C. Lau ,  Jason Wei ,  Tsyr-Chyang Ho ,  Samir A. Patel ,  Yiu-Fai Chan

    发明人： Benedict C. Lau ,  Jason Wei ,  Tsyr-Chyang Ho ,  Samir A. Patel ,  Yiu-Fai Chan

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4072

    摘要： An interface circuit providing a high speed bus. According to one embodiment, the interface circuitry includes a plurality of I/O pins coupled to a plurality of bus drivers, wherein each bus driver is configured to adjust the rise time, fall time, and drive strength of outputs signal on the I/O pins based on process-voltage-temperature ("PVT") conditions. The circuitry used to adjust the I/O outputs includes a slew rate control circuit, a current control circuit, and a delay lock loop ("DLL").

    摘要翻译： 提供高速总线的接口电路。 根据一个实施例，接口电路包括耦合到多个总线驱动器的多个I / O引脚，其中每个总线驱动器被配置为调整I / O上的输出信号的上升时间，下降时间和驱动强度 基于过程电压 - 温度（“PVT”）条件的引脚。 用于调整I / O输出的电路包括压摆率控制电路，电流控制电路和延迟锁定环（“DLL”）。

    Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits
    9.
    发明授权
    Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits 失效
    可编程宏单元使用eprom或eeprom晶体管进行可编程逻辑电路中的架构控制

    公开(公告)号：US4713792A

    公开(公告)日：1987-12-15

    申请号：US742089

    申请日：1985-06-06

    申请人： Robert F. Hartmann ,  Yiu-Fai Chan ,  Robert J. Frankovich ,  Jung-Hsing Ou ,  Hock C. So ,  Sau-Ching Wong

    发明人： Robert F. Hartmann ,  Yiu-Fai Chan ,  Robert J. Frankovich ,  Jung-Hsing Ou ,  Hock C. So ,  Sau-Ching Wong

    IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/82 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H03K17/693 ,  H03K19/173 ,  H03K19/177 ,  G06F1/00

    CPC分类号： H03K19/1736 ,  H03K17/693 ,  H03K19/1737

    摘要： A programmable macrocell 28 for use in an integrated circuit device including an electronic circuit 32 responsive to control signals and operative to perform particular operations selected by the control signals on input data signals and to develop commensurate output signals, and one or more architecture control circuits 30 each including a programmable EPROM device 34 which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state, a read and write control circuit 36 responsive to input program data signals and a corresponding address signal and operative to program the EPROM device 34 by applying a programming potential thereto, and a sensing circuit 38 for sensing the programmed or unprogrammed status of the EPROM device 34 and for developing a commensurate control signal for input to the electronic circuit 32.

    摘要翻译： 一种用于集成电路设备的可编程宏单元28，其包括响应于控制信号的电子电路32，并且可操作以执行由输入数据信号上的控制信号选择的特定操作并且开发相应的输出信号，以及一个或多个架构控制电路30 每个都包括一个可编程EPROM器件34，当被编程时产生第一状态的逻辑信号，并且当未编程产生第二状态的逻辑信号时，读和写控制电路36响应输入的程序数据信号和对应的地址信号， 通过向其施加编程电位来对EPROM器件34进行编程;以及感测电路38，用于感测EPROM器件34的编程状态或未编程状态，并用于形成相应的控制信号以输入到电子电路32。