公开(公告)号：US5057886A

公开(公告)日：1991-10-15

申请号：US288542

申请日：1988-12-21

申请人： Bert R. Riemenschneider ,  Howard L. Tigelaar

发明人： Bert R. Riemenschneider ,  Howard L. Tigelaar

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L29/7885

摘要： A non-volatile memory is provided which provides a floating gate (42) disposed over control gate (38) in order to increase the coupling therebetween. The degree of coupling may be varied by adjusting the area of the floating gate formed over the control gate relative to the area of the floating gate over the substrate.

摘要翻译： 提供了一种非易失性存储器，其提供设置在控制栅极（38）上方的浮动栅极（42），以便增加它们之间的耦合。 可以通过调节在控制栅极上形成的浮栅的面积相对于衬底上浮动栅极的面积来改变耦合度。

公开(公告)号：US4839705A

公开(公告)日：1989-06-13

申请号：US133709

申请日：1987-12-16

申请人： Howard L. Tigelaar ,  Allan T. Mitchell ,  Bert R. Riemenschneider ,  James L. Paterson

发明人： Howard L. Tigelaar ,  Allan T. Mitchell ,  Bert R. Riemenschneider ,  James L. Paterson

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7881

摘要： An X-cell EEPROM array includes a plurality of common source regions (50) that each border on four gate regions (46), both formed at a face of a semiconductor substrate (10). Each gate region (46) further adjoins a common drain region (52). Each drain region (52) is a common drain for two EEPROM select and memory transistors. A common erase region (54) is implanted into the semiconductor layer (10) in a position remote from the source regions (50) and the drain regions (52). Four floating gate electrodes (40) extend over tunnel windows (22) that are formed on the semiconductor layer (10) in positions adjacent a single erase region (54). An integral contact (64) is made through multilevel oxide (56, 58) from a metal erase line (70) to each erase region (54).

摘要翻译： X单元EEPROM阵列包括在半导体衬底（10）的表面上形成的多个公共源极区域（50），每个共同源极区域（50）在四个栅极区域（46）上边界。 每个栅极区域（46）还与公共漏极区域（52）相邻。 每个漏极区域（52）是两个EEPROM选择和存储晶体管的公共漏极。 在远离源极区域（50）和漏极区域（52）的位置，将公共擦除区域（54）注入到半导体层（10）中。 四个浮栅电极（40）在与单个擦除区域（54）相邻的位置上形成在半导体层（10）上的隧道窗（22）上延伸。 通过从金属擦除线（70）到每个擦除区域（54）的多层氧化物（56,58）制成整体触点（64）。

公开(公告)号：US5595922A

公开(公告)日：1997-01-21

申请号：US330655

申请日：1994-10-28

申请人： Howard L. Tigelaar ,  Bert R. Riemenschneider ,  Richard A. Chapman ,  Andrew T. Appel

发明人： Howard L. Tigelaar ,  Bert R. Riemenschneider ,  Richard A. Chapman ,  Andrew T. Appel

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28211 ,  Y10S438/911 ,  Y10S438/981

摘要： One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

摘要翻译： 本发明的一个实施例是在单个衬底（14）上同时形成高电压（12）和低电压（10）器件的方法，所述方法包括：在衬底上形成薄的氧化物层（18） 所述薄氧化物层具有用于所述低压器件的栅极氧化物的期望厚度; 选择性地形成用于高电压器件的栅极结构（30），薄氧化物位于栅极结构和衬底之间; 并且在栅极结构下选择性地增厚薄氧化物，同时将用于低电压器件的薄氧化物层保持在期望的厚度。

公开(公告)号：US4829019A

公开(公告)日：1989-05-09

申请号：US48719

申请日：1987-05-12

申请人： Allan T. Mitchell ,  Howard L. Tigelaar ,  Bert R. Riemenschneider

发明人： Allan T. Mitchell ,  Howard L. Tigelaar ,  Bert R. Riemenschneider

IPC分类号： H01L21/76 ,  H01L21/266 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L21/266 ,  H01L21/76216

摘要： A method of forming semiconductor devices wherein a gap is formed beneath the field oxide between the channel stop implant and source/drain regions in the moat or active element region to prevent or minimize encroachment of channel stop impurity toward the source/drain regions to form spurious pn junctions and/or reduce the active element region.

摘要翻译： 一种形成半导体器件的方法，其中在沟道阻挡注入和沟槽或有源元件区域中的源极/漏极区之间的场氧化物之下形成间隙，以防止或最小化沟道阻挡杂质侵入源/漏区以形成假 pn结和/或减少有源元件区域。

公开(公告)号：US4827323A

公开(公告)日：1989-05-02

申请号：US195346

申请日：1988-05-12

申请人： Howard L. Tigelaar ,  Bert R. Riemenschneider

发明人： Howard L. Tigelaar ,  Bert R. Riemenschneider

IPC分类号： H01L21/02 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/78 ,  H01G4/06 ,  H01L23/48 ,  H01L27/02

CPC分类号： H01L27/1085 ,  H01L21/8229 ,  H01L27/10805 ,  H01L28/40 ,  H01L29/945

摘要： The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates. The area etched away is then filled with a suitable dielectric and a contact is made to the unetched interleaved plates. Thus a fully interleaved capacitor is provided using relatively simple fabrication techniques while still providing increased capacitance.

摘要翻译： 本发明提供了一种用于制造该结构的结构和方法，该结构在占用集成电路的最小表面积的同时提供了比现有技术更大的电容。 本发明通过交错多个电容器板来提供增加的电容，同时占据与现有技术的电容器相同的表面积，从而提供本发明提供的电容的一部分。 本发明通过提供一种电容器堆叠来制造，该电容器堆叠包括可被选择性蚀刻并由适当的介电材料分离的材料的交错板。 当一组交错板被蚀刻时，屏蔽该堆叠的一部分。 交错板的蚀刻部分由合适的电介质填充，并且与剩余的板接触。 然后将堆叠的不同部分暴露于蚀刻另一组交错板的蚀刻。 然后用合适的电介质填充被蚀刻的区域，并且对未蚀刻的交错板进行接触。 因此，使用相对简单的制造技术提供完全交错的电容器，同时仍然提供增加的电容。

公开(公告)号：US4685197A

公开(公告)日：1987-08-11

申请号：US781846

申请日：1986-01-07

申请人： Howard L. Tigelaar ,  Bert R. Riemenschneider

发明人： Howard L. Tigelaar ,  Bert R. Riemenschneider

IPC分类号： H01L21/02 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L27/10 ,  G11C11/34 ,  H01L27/04

CPC分类号： H01L27/1085 ,  H01L21/8229 ,  H01L27/10805 ,  H01L28/40 ,  H01L29/945 ,  Y10T29/435

摘要： The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates. The area etched away is then filled with a suitable dielectric and a contact is made to the unetched interleaved plates. Thus a fully interleaved capacitor is provided using relatively simple fabrication techniques while still providing increased capacitance.

摘要翻译： 本发明提供了一种用于制造该结构的结构和方法，该结构在占用集成电路的最小表面积的同时提供了比现有技术更大的电容。 本发明通过交错多个电容器板来提供增加的电容，同时占据与现有技术的电容器相同的表面积，从而提供本发明提供的电容的一部分。 本发明通过提供一种电容器堆叠来制造，该电容器堆叠包括可被选择性蚀刻并由适当的介电材料分离的材料的交错板。 当一组交错板被蚀刻时，屏蔽该堆叠的一部分。 交错板的蚀刻部分由合适的电介质填充，并且与剩余的板接触。 然后将堆叠的不同部分暴露于蚀刻另一组交错板的蚀刻。 然后用合适的电介质填充被蚀刻的区域，并且对未蚀刻的交错板进行接触。 因此，使用相对简单的制造技术提供完全交错的电容器，同时仍然提供增加的电容。

公开(公告)号：US07752518B2

公开(公告)日：2010-07-06

申请号：US12030365

申请日：2008-02-13

申请人： Cloves R. Cleavelin ,  Andrew Marshall ,  Stephanie W. Butler ,  Howard L. Tigelaar

发明人： Cloves R. Cleavelin ,  Andrew Marshall ,  Stephanie W. Butler ,  Howard L. Tigelaar

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/76 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/1208

摘要： An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

公开(公告)号：US20090204861A1

公开(公告)日：2009-08-13

申请号：US12030365

申请日：2008-02-13

申请人： Cloves R. Cleavelin ,  Andrew Marshall ,  Stephanie W. Butler ,  Howard L. Tigelaar

发明人： Cloves R. Cleavelin ,  Andrew Marshall ,  Stephanie W. Butler ,  Howard L. Tigelaar

IPC分类号： G01R31/28

CPC分类号： G11C29/76 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/1208

摘要： An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

摘要翻译： 集成电路（IC），IC的测试方法和从含有内置自检（BIST）电路的IC读取测试结果的方法。 在一个实施例中，IC包括：（1）外部测试总线接口，（2）耦合到外部测试总线接口的读写存储器，（3）耦合到外部测试总线的其他电路和（4）BIST电路 接口，读写存储器和其他电路，并且被配置为测试读写存储器以识别其中的良好数据块，将读写存储器中的预定数据块存储到指向良好数据块的多个实例中 ，至少对其他电路进行测试，并将至少一些测试结果存储在良好的数据块中。

公开(公告)号：US06180424B2

公开(公告)日：2001-01-30

申请号：US09203970

申请日：1998-12-02

申请人： Howard L. Tigelaar ,  Richard L. Guldi

发明人： Howard L. Tigelaar ,  Richard L. Guldi

IPC分类号： H01L2166

CPC分类号： H01L21/67259 ,  G01R31/2831 ,  Y10S414/136

摘要： A method of testing semiconductor wafers wherein a cassette (3) containing a plurality of semiconductor wafers for fabrication is provided. The location and orientation of each of the wafers within the cassette is determined and at least one processing step is performed on the wafers. At least one of an alteration of the location in the cassette (5) and orientation of the wafers (7) is provided and at least one additional processing step is performed on the wafers. At least one of an alteration of the location and orientation of the wafers is provided including alteration of the location or orientation of the wafers if not yet altered. At least one like parameter of each of the wafers is measured (9). The variation across the wafer of the at least one parameter is correlated with the orientation and the location on a wafer by wafer basis and processing errors are determined from the step of correlating which can be used to alter and reduce variation in the fabrication process.

摘要翻译： 一种测试半导体晶片的方法，其中提供包含用于制造的多个半导体晶片的盒（3）。 确定盒内每个晶片的位置和取向，并在晶片上执行至​​少一个处理步骤。 提供盒（5）中的位置的改变和晶片（7）的取向中的至少一个，并且在晶片上执行至​​少一个附加处理步骤。 提供了晶片的位置和取向的改变中的至少一个，包括晶片的位置或取向的改变，如果还没有改变。 测量每个晶片的至少一个相似的参数（9）。 晶片上的至少一个参数的变化与晶片的取向和位置相关，并且根据相关步骤确定处理误差，哪些可用于改变和减少制造过程中的变化。

公开(公告)号：US5200350A

公开(公告)日：1993-04-06

申请号：US736337

申请日：1991-07-26

申请人： Manzur Gill ,  Howard L. Tigelaar

发明人： Manzur Gill ,  Howard L. Tigelaar

IPC分类号： H01L27/115

CPC分类号： H01L27/115

摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

摘要翻译： 一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。 位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。 阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。 字线之间和位线之间的隔离是厚场氧化物区域。 一个厚场氧化物条将每个接地导线/位线对分开。 字线可以由具有低电阻率的硅化多晶或其它材料形成。 通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。 所得到的结构是可编程存储器单元的密集交叉点阵列。