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    Laser ablation for integrated circuit fabrication
    2.
    发明授权
    Laser ablation for integrated circuit fabrication 有权
    激光烧蚀用于集成电路制造

    公开(公告)号：US08419895B2

    公开(公告)日：2013-04-16

    申请号：US12788843

    申请日：2010-05-27

    申请人： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

    发明人： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

    IPC分类号： B32B38/10

    CPC分类号： H01L21/6835 ,  B23K26/361 ,  H01L2221/68381 ,  Y10T156/1111 ,  Y10T156/1158 ,  Y10T156/1917

    摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

    摘要翻译： 一种用于从晶片释放处理器的方法，包括集成电路（IC）的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。 一种用于从晶片释放处理器的系统，包括IC的晶片包括使用包含聚合物的粘合剂附接到晶片的处理器; 边缘处理模块，所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器，激光器被配置为通过处理器消融粘合剂。

    Laser Ablation for Integrated Circuit Fabrication
    3.
    发明申请
    Laser Ablation for Integrated Circuit Fabrication 有权
    激光消融用于集成电路制造

    公开(公告)号：US20110290406A1

    公开(公告)日：2011-12-01

    申请号：US12788843

    申请日：2010-05-27

    申请人： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

    发明人： Bing Dang ,  John Knickerbocker ,  Aparna Prabhakar ,  Peter Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

    IPC分类号： B29C65/16

    CPC分类号： H01L21/6835 ,  B23K26/361 ,  H01L2221/68381 ,  Y10T156/1111 ,  Y10T156/1158 ,  Y10T156/1917

    摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC) includes attaching the handler to the wafer using an adhesive comprising a polymer; performing edge processing to remove an excess portion of the adhesive from an edge of the handler and wafer; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer. A system for releasing a handler from a wafer, the wafer comprising an IC includes a handler attached to a wafer using an adhesive comprising a polymer; an edge processing module, the edge processing module configured to remove an excess portion of the adhesive from the edge of the handler and wafer; and a laser, the laser configured to ablate the adhesive through the handler.

    摘要翻译： 一种用于从晶片释放处理器的方法，包括集成电路（IC）的晶片包括使用包含聚合物的粘合剂将处理器附接到晶片; 执行边缘处理以从处理器和晶片的边缘去除多余的粘合剂部分; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。 一种用于从晶片释放处理器的系统，包括IC的晶片包括使用包含聚合物的粘合剂连接到晶片的处理器; 边缘处理模块，所述边缘处理模块被配置为从所述处理器和晶片的边缘去除所述粘合剂的多余部分; 和激光器，激光器被配置为通过处理器消融粘合剂。

    STRIPED ON-CHIP INDUCTOR
    7.
    发明申请
    STRIPED ON-CHIP INDUCTOR 有权
    带状片上电感器

    公开(公告)号：US20120223411A1

    公开(公告)日：2012-09-06

    申请号：US13469464

    申请日：2012-05-11

    申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

    发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

    IPC分类号： H01L29/86 ,  H01L21/02

    CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

    摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

    Striped on-chip inductor
    8.
    发明授权
    Striped on-chip inductor 有权
    条形片上电感

    公开(公告)号：US08227891B2

    公开(公告)日：2012-07-24

    申请号：US12362877

    申请日：2009-01-30

    申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

    发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

    IPC分类号： H01L21/00

    CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

    摘要翻译： 提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

    SYSTEM AND METHOD FOR MODIFICATION AND/OR SMOOTHING OF TISSUE WITH LASER ABLATION
    9.
    发明申请
    SYSTEM AND METHOD FOR MODIFICATION AND/OR SMOOTHING OF TISSUE WITH LASER ABLATION 审中-公开
    用于激光消融的组织修饰和/或吸收的系统和方法

    公开(公告)号：US20130190742A1

    公开(公告)日：2013-07-25

    申请号：US13640588

    申请日：2011-04-12

    申请人： Daniel Patrick Connors ,  Jerome Felsenstein ,  Robert E. Trzcinski ,  James J. Wynne ,  Donna S. Zupanski-Nielsen

    发明人： Daniel Patrick Connors ,  Jerome Felsenstein ,  Robert E. Trzcinski ,  James J. Wynne ,  Donna S. Zupanski-Nielsen

    IPC分类号： A61B18/20

    CPC分类号： A61B18/20 ,  A61B2018/207

    摘要： Disclosed is an improved system and method for efficiently removing tissue using laser ablation. A first laser emits a first laser beam with a variable first integrated fluence sufficient to ablate tissue. The first laser beam is movably positioned over one or more surfaces of the tissue and the first integrated fluence varies over different levels with position, so different thicknesses of tissue are ablated at different surface positions in order to modify the contour of the surface of the tissue. Modifications include tissue smoothing, removing, feathering, sharpening, and roughening. In one preferred embodiment the tissue is eschar that is removed, unveiling viable tissue. In alternate preferred embodiments, one or more additional lasers beams with different wavelengths, with integrated fluence sufficient to ablate tissue, are moved over the surface of the tissue until a second ablation reaches a second self-termination point, e.g., determined by affects of chemicals below the termination point that absorb the second laser beam without producing the temperature increase necessary for ablation to continue.

    摘要翻译： 公开了一种使用激光烧蚀有效去除组织的改进的系统和方法。 第一激光器发射具有足以消融组织的可变的第一积分能量密度的第一激光束。 第一激光束可移动地定位在组织的一个或多个表面上，并且第一集成能量密度在具有位置的不同水平上变化，因此不同厚度的组织在不同的表面位置被消融，以便修改组织表面的轮廓 。 修改包括组织平滑，去除，羽化，磨锐和粗糙化。 在一个优选实施方案中，组织是被除去的焦痂，揭开活组织。 在替代优选实施例中，具有足以消融组织的积分能量密度的具有不同波长的一个或多个附加激光束在组织的表面上移动，直到第二消融达到第二自终止点，例如由化学物质的影响确定 低于吸收第二激光束的终止点，而不产生消融所需的温度升高。

    HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN
    10.
    发明申请
    HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN 有权
    高密度片上电容设计

    公开(公告)号：US20090152612A1

    公开(公告)日：2009-06-18

    申请号：US12371756

    申请日：2009-02-16

    申请人： Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

    发明人： Jonghae Kim ,  Moon J. Kim ,  Jean-Olivier Plouchart ,  Robert E. Trzcinski

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0811 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

    摘要翻译： 设置安装在半导体芯片上的电容电路组件及其形成方法。 多个发散电容器设置在第一和第二端口之间的并联电路连接中，多个提供至少一个金属氧化物硅电容器和至少一个垂直本机电容器或金属绝缘体金属电容器。 组件具有垂直取向，金属氧化物硅电容器位于底部并限定占地面积，中间垂直本机电容器具有多个水平金属层，包括多个平行的正极板，与多个平行的负极板交替 。 在另一方面，垂直不对称取向提供减小的总寄生电容。