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    Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer
    4.
    发明申请
    Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer 有权
    使用牺牲金属氧化物层形成双镶嵌金属互连的方法

    公开(公告)号：US20050124149A1

    公开(公告)日：2005-06-09

    申请号：US10939930

    申请日：2004-09-13

    申请人： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

    发明人： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

    IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76808 ,  H01L21/31144

    摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.

    摘要翻译： 提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。 该方法包括制备半导体衬底。 在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。 在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。 在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。 使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

    Method of forming dual damascene interconnection using low-k dielectric material
    6.
    发明授权
    Method of forming dual damascene interconnection using low-k dielectric material 有权
    使用低k介电材料形成双镶嵌互连的方法

    公开(公告)号：US07022600B2

    公开(公告)日：2006-04-04

    申请号：US10437806

    申请日：2003-05-14

    申请人： Jae-Hak Kim ,  Soo-Geun Lee ,  Ki-Kwan Park ,  Kyoung-Woo Lee

    发明人： Jae-Hak Kim ,  Soo-Geun Lee ,  Ki-Kwan Park ,  Kyoung-Woo Lee

    IPC分类号： H01L21/475

    CPC分类号： H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

    摘要： In order to avoid a faulty pattern resulting from a photoresist tail being formed due to a step difference of an upper hard mask layer when a dual hard mask layer is used, a planarization layer is formed following patterning of the upper hard mask layer. In this manner, a photoresist pattern is formed without the creation of a photoresist tail. Alternatively, a single hard mask layer and a planarization layer are substituted for the dual lower hard mask layer and an upper hard mask layer, respectively. In this manner, it is therefore possible to form a photoresist pattern without a photoresist tail being formed during photolithographic processes. In order to prevent formation of a facet, the planarization layer is thickly formed or, alternatively, the hard mask layer is etched using the photoresist pattern.

    摘要翻译： 为了避免当使用双硬掩模层时由于上部硬掩模层的阶差而形成的光致抗蚀剂尾部产生的故障图案，在上部硬掩模层的图案化之后形成平坦化层。 以这种方式，形成光致抗蚀剂图案而不产生光致抗蚀剂尾部。 或者，单个硬掩模层和平坦化层分别代替双下硬掩模层和上硬掩模层。 以这种方式，因此可以在光刻工艺期间形成光致抗蚀剂图案而不形成光致抗蚀剂尾部。 为了防止小面的形成，平坦化层被厚地形成，或者使用光致抗蚀剂图案蚀刻硬掩模层。

    Method of forming a via contact structure using a dual damascene process
    7.
    发明申请
    Method of forming a via contact structure using a dual damascene process 有权
    使用双镶嵌工艺形成通孔接触结构的方法

    公开(公告)号：US20060003574A1

    公开(公告)日：2006-01-05

    申请号：US11099534

    申请日：2005-04-06

    申请人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

    发明人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808

    摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

    摘要翻译： 公开了一种使用双镶嵌工艺形成通孔接触结构的方法。 根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。 牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。 在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。 根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。 在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

    Method of forming interconnection lines for semiconductor device
    8.
    发明申请
    Method of forming interconnection lines for semiconductor device 失效
    形成半导体器件互连线的方法

    公开(公告)号：US20050176236A1

    公开(公告)日：2005-08-11

    申请号：US11049730

    申请日：2005-02-04

    申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

    IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

    摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

    摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。