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公开(公告)号：US20110133280A1
公开(公告)日：2011-06-09
申请号：US12631148
申请日：2009-12-04
IPC分类号： H01L29/786 , H01L21/336 , H01L29/78
CPC分类号： H01L29/78696 , H01L29/42392
摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.
摘要翻译： 产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。 该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。 第一栅极氧化物比第二栅极氧化物厚。 该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和 第一线和第二线内的漏极区。
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公开(公告)号：US08008146B2
公开(公告)日：2011-08-30
申请号：US12631148
申请日：2009-12-04
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392
摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.
摘要翻译： 产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。 该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。 第一栅极氧化物比第二栅极氧化物厚。 该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和 第一线和第二线内的漏极区。
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公开(公告)号：US20120145650A1
公开(公告)日：2012-06-14
申请号：US12966370
申请日：2010-12-13
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。
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公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。
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5.发明授权Nanowire stress sensors, stress sensor integrated circuits, and design structures for a stress sensor integrated circuit 有权纳米线应力传感器，应力传感器集成电路和应力传感器集成电路的设计结构公开(公告)号：US08614492B2
公开(公告)日：2013-12-24
申请号：US12605523
申请日：2009-10-26
申请人： Andres Bryant , Oki Gunawan , Shih-Hsien Lo , Jeffrey W Sleight
发明人： Andres Bryant , Oki Gunawan , Shih-Hsien Lo , Jeffrey W Sleight
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , G01B7/16 , G01B7/18 , H01L29/045 , H01L29/0665 , H01L29/66439 , H01L29/775 , Y10S977/724 , Y10S977/938 , Y10S977/956
摘要： Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.
摘要翻译： 使用一个或多个纳米线场效应晶体管作为应力敏感元件的应力传感器和应力传感器集成电路，以及体现在用于设计，制造或测试集成电路的机器可读介质中的应力传感器集成电路的设计结构，以及 相关方法。 应力传感器和应力传感器集成电路包括一对或多对栅极全环场效应晶体管，其包括一个或多个纳米线作为沟道区。 每个场效应晶体管的纳米线被配置为响应于从物体传递的机械应力而改变长度。 与场效应晶体管的电压输出差异表示转移的机械应力的大小。
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6.发明申请Nanowire Stress Sensors and Stress Sensor Integrated Circuits, Design Structures for a Stress Sensor Integrated Circuit, and Related Methods 有权纳米线应力传感器和应力传感器集成电路，应力传感器集成电路的设计结构及相关方法公开(公告)号：US20110095267A1
公开(公告)日：2011-04-28
申请号：US12605523
申请日：2009-10-26
申请人： Andres Bryant , Oki Gunawan , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Andres Bryant , Oki Gunawan , Shih-Hsien Lo , Jeffrey W. Sleight
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y40/00 , G01B7/16 , G01B7/18 , H01L29/045 , H01L29/0665 , H01L29/66439 , H01L29/775 , Y10S977/724 , Y10S977/938 , Y10S977/956
摘要： Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.
摘要翻译： 使用一个或多个纳米线场效应晶体管作为应力敏感元件的应力传感器和应力传感器集成电路，以及体现在用于设计，制造或测试集成电路的机器可读介质中的应力传感器集成电路的设计结构，以及 相关方法。 应力传感器和应力传感器集成电路包括一对或多对栅极全环场效应晶体管，其包括一个或多个纳米线作为沟道区。 每个场效应晶体管的纳米线被配置为响应于从物体传递的机械应力而改变长度。 与场效应晶体管的电压输出差异表示转移的机械应力的大小。
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7.发明申请HIGH DENSITY BUTTED JUNCTION CMOS INVERTER, AND MAKING AND LAYOUT OF SAME 审中-公开高密度指针式CMOS反相器，以及其制造和布局公开(公告)号：US20110291193A1
公开(公告)日：2011-12-01
申请号：US12788362
申请日：2010-05-27
CPC分类号： H01L27/1203 , H01L21/26586 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.
摘要翻译： 形成在SOI衬底上的高密度，不对称对接结CMOS反相器可以包括：非对称p-FET，其仅在p-FET的源极侧包括卤素注入; 一个不对称的n-FET，其仅在n-FET的源极侧包括一个卤素注入; 以及包括所述SOI衬底的区域的对接结，其中所述非对称n-FET的漏极区域和所述非对称p-FET的漏极区域直接物理接触。 可以通过以离子吸收结构覆盖CMOS反相器的第一FET的顺序过程形成非对称晕环植入物，并且仅向第二FET的源极侧施加成角度的离子辐射，去除离子吸收结构，覆盖第一 FET，具有第二离子吸收结构，并且仅向第二FET的源极侧施加成角度的离子辐射。 CMOS集成电路的布局显示可能需要高密度，不对称对接结CMOS反相器和其他CMOS电路的另一个接地规则的一个接地规则。
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公开(公告)号：US07981772B2
公开(公告)日：2011-07-19
申请号：US12344696
申请日：2008-12-29
IPC分类号： H01L21/3213
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/16 , H01L29/161 , Y10S977/888
摘要： A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.
摘要翻译： 示出了制造纳米结构的方法，更具体地说，涉及制造硅纳米线的方法。 制造纳米线的方法包括在衬底上形成SiX材料和材料Si的夹层结构，并蚀刻夹层结构以暴露Si材料和SiX材料的侧壁。 该方法还包括蚀刻SiX材料以暴露Si材料的部分并蚀刻Si材料的暴露部分。 该方法还包括分离Si材料以形成硅纳米线。
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公开(公告)号：US09768304B2
公开(公告)日：2017-09-19
申请号：US13492108
申请日：2012-06-08
IPC分类号： H01L21/20 , H01L29/78 , H01L21/8238 , H01L27/12 , H01L29/10 , H01L21/3115 , H01L21/762 , H01L29/66
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
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10.发明授权Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors 有权集成电路结构，其包括一个或多个不对称场效应晶体管作为具有堆叠对称场效应晶体管的电子电路的功率门公开(公告)号：US08941180B2
公开(公告)日：2015-01-27
申请号：US13044872
申请日：2011-03-10
IPC分类号： H01L27/02 , H01L27/12 , H01L21/8234 , H01L29/786 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/78624
摘要： Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin).
摘要翻译： 公开了具有不对称FET作为电子电路的功率门的集成电路，其具有至少两个堆叠的对称场效应晶体管。 非对称FET具有不对称的卤素配置（即，具有比漏极侧卤素更高的掺杂剂浓度的单个源极卤素或源极卤素）和非对称源极/漏极延伸配置（即，源极延伸可以 通过栅极结构比漏极延伸更大程度地重叠和/或源极延伸可以具有比漏极延伸更高的掺杂剂浓度）。 结果，不对称FET具有低截止电流。 在操作中，当电子电路处于待机状态时，不对称FET被关闭，并且由于低关断电流（Ioff），有效地减少了来自电子电路的待机漏电流。 另外，避免使用电子电路内的层叠的非对称场效应晶体管本身可以防止由于线性漏极电流（Idlin）的降低导致的性能劣化。
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