公开(公告)号：US20050094432A1

公开(公告)日：2005-05-05

申请号：US11001231

申请日：2004-12-01

申请人： Brian Johnson ,  Brent Keeth ,  Jeffery Janzen ,  Troy Manning ,  Chris Martin

发明人： Brian Johnson ,  Brent Keeth ,  Jeffery Janzen ,  Troy Manning ,  Chris Martin

IPC分类号： G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C11/00

CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

公开(公告)号：US20080089158A1

公开(公告)日：2008-04-17

申请号：US11999383

申请日：2007-12-04

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US20060045206A1

公开(公告)日：2006-03-02

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L27/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US20050122789A1

公开(公告)日：2005-06-09

申请号：US11031437

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C5/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US20070058469A1

公开(公告)日：2007-03-15

申请号：US11595515

申请日：2006-11-08

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US20060203938A1

公开(公告)日：2006-09-14

申请号：US11433322

申请日：2006-05-11

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L25/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US20060082478A1

公开(公告)日：2006-04-20

申请号：US11284498

申请日：2005-11-21

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： H03M9/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US20050122814A1

公开(公告)日：2005-06-09

申请号：US11030844

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US20070115712A1

公开(公告)日：2007-05-24

申请号：US11654435

申请日：2007-01-16

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/06

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

摘要翻译： 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US20050007807A1

公开(公告)日：2005-01-13

申请号：US10910980

申请日：2004-08-03

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.