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    SEMICONDUCTOR DEVICES INCLUDING EPITAXIAL LAYERS AND RELATED METHODS
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING EPITAXIAL LAYERS AND RELATED METHODS 审中-公开
    包括外延层的半导体器件及相关方法

    公开(公告)号：US20130009221A1

    公开(公告)日：2013-01-10

    申请号：US13608350

    申请日：2012-09-10

    申请人： Brett Adam Hull ,  Qingchun Zhang

    发明人： Brett Adam Hull ,  Qingchun Zhang

    IPC分类号： H01L21/20 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7828

    摘要： A semiconductor device may include a semiconductor layer having a first conductivity type, a well region of a second conductivity type in the semiconductor layer wherein the first and second conductivity types are different, and a terminal region of the first conductivity type in the well region. An epitaxial semiconductor layer may be on the surface of the semiconductor layer including the well region and the terminal region with the epitaxial semiconductor layer having the first conductivity type across the well and terminal regions. A gate electrode may be on the epitaxial semiconductor layer so that the epitaxial semiconductor layer is between the gate electrode and portions of the well region surrounding the terminal region at the surface of the semiconductor layer.

    摘要翻译： 半导体器件可以包括具有第一导电类型的半导体层，在半导体层中的第一和第二导电类型不同的第二导电类型的阱区域以及阱区域中的第一导电类型的端子区域。 外延半导体层可以在包括阱区和半导体层的表面上，其中外延半导体层具有穿过阱和端子区的第一导电类型。 栅电极可以在外延半导体层上，使得外延半导体层位于半导体层的表面处的栅电极和围绕端区的阱区的部分之间。

    Methods of Forming Semiconductor Devices Including Epitaxial Layers and Related Structures
    3.
    发明申请
    Methods of Forming Semiconductor Devices Including Epitaxial Layers and Related Structures 有权
    形成包括外延层和相关结构的半导体器件的方法

    公开(公告)号：US20100244047A1

    公开(公告)日：2010-09-30

    申请号：US12412448

    申请日：2009-03-27

    申请人： Brett Adam Hull ,  Qingchun Zhang

    发明人： Brett Adam Hull ,  Qingchun Zhang

    IPC分类号： H01L29/161 ,  H01L21/04

    CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7828

    摘要： A method of forming a semiconductor device may include forming a terminal region of a first conductivity type within a semiconductor layer of the first conductivity type. A well region of a second conductivity type may be formed within the semiconductor layer wherein the well region is adjacent at least portions of the terminal region within the semiconductor layer, a depth of the well region into the semiconductor layer may be greater than a depth of the terminal region into the semiconductor layer, and the first and second conductivity types may be different. An epitaxial semiconductor layer may be formed on the semiconductor layer, and a terminal contact region of the first conductivity type may be formed in the epitaxial semiconductor layer with the terminal contact region providing electrical contact with the terminal region. In addition, an ohmic contact may be formed on the terminal contact region. Related structures are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在第一导电类型的半导体层内形成第一导电类型的端子区域。 可以在半导体层内形成第二导电类型的阱区，其中阱区与半导体层内的端区的至少一部分相邻，进入半导体层的阱区的深度可以大于 端子区域进入半导体层，并且第一和第二导电类型可以不同。 可以在半导体层上形成外延半导体层，并且可以在外延半导体层中形成第一导电类型的端子接触区域，其中端子接触区域与端子区域提供电接触。 此外，可以在端子接触区域上形成欧姆接触。 还讨论了相关结构。

    Methods of forming semiconductor devices including epitaxial layers and related structures
    4.
    发明授权
    Methods of forming semiconductor devices including epitaxial layers and related structures 有权
    形成包括外延层和相关结构的半导体器件的方法

    公开(公告)号：US08288220B2

    公开(公告)日：2012-10-16

    申请号：US12412448

    申请日：2009-03-27

    申请人： Brett Adam Hull ,  Qingchun Zhang

    发明人： Brett Adam Hull ,  Qingchun Zhang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/0847 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7828

    摘要： A method of forming a semiconductor device may include forming a terminal region of a first conductivity type within a semiconductor layer of the first conductivity type. A well region of a second conductivity type may be formed within the semiconductor layer wherein the well region is adjacent at least portions of the terminal region within the semiconductor layer, a depth of the well region into the semiconductor layer may be greater than a depth of the terminal region into the semiconductor layer, and the first and second conductivity types may be different. An epitaxial semiconductor layer may be formed on the semiconductor layer, and a terminal contact region of the first conductivity type may be formed in the epitaxial semiconductor layer with the terminal contact region providing electrical contact with the terminal region. In addition, an ohmic contact may be formed on the terminal contact region. Related structures are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括在第一导电类型的半导体层内形成第一导电类型的端子区域。 可以在半导体层内形成第二导电类型的阱区，其中阱区与半导体层内的端区的至少一部分相邻，进入半导体层的阱区的深度可以大于 端子区域进入半导体层，并且第一和第二导电类型可以不同。 可以在半导体层上形成外延半导体层，并且可以在外延半导体层中形成第一导电类型的端子接触区域，其中端子接触区域与端子区域提供电接触。 此外，可以在端子接触区域上形成欧姆接触。 还讨论了相关结构。

    SiC devices with high blocking voltage terminated by a negative bevel
    5.
    发明授权
    SiC devices with high blocking voltage terminated by a negative bevel 有权
    具有高阻断电压的SiC器件由负斜角端接

    公开(公告)号：US09337268B2

    公开(公告)日：2016-05-10

    申请号：US13108366

    申请日：2011-05-16

    申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L29/16

    CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

    摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

    摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。

    Electronic device structure with a semiconductor ledge layer for surface passivation
    6.
    发明授权
    Electronic device structure with a semiconductor ledge layer for surface passivation 有权
    具有用于表面钝化的半导体凸缘层的电子器件结构

    公开(公告)号：US08809904B2

    公开(公告)日：2014-08-19

    申请号：US12843113

    申请日：2010-07-26

    申请人： Qingchun Zhang ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Anant Agarwal

    IPC分类号： H01L29/36

    CPC分类号： H01L29/66378 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66234 ,  H01L29/66363 ,  H01L29/744

    摘要： Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

    摘要翻译： 公开了包括用于表面钝化的半导体凸缘层的电子器件结构及其制造方法。 在一个实施例中，电子器件包括具有交替掺杂类型的期望半导体材料的多个半导体层。 半导体层包括第一掺杂类型的基极层，其包括形成电子器件的第一接触区域的高度掺杂的阱和在基底层上的第二掺杂类型的一个或多个接触层，其被蚀刻以形成第二掺杂阱 电子设备的接触区域。 一个或多个接触层的蚀刻在基层的表面上引起显着的晶体损伤，并因此导致界面电荷。 为了钝化基底层的表面，半导体材料的半导体凸缘层至少在基底层的表面上外延生长。

    Mesa termination structures for power semiconductor devices and methods of forming power semiconductor devices with mesa termination structures
    9.
    发明授权
    Mesa termination structures for power semiconductor devices and methods of forming power semiconductor devices with mesa termination structures 有权
    用于功率半导体器件的Mesa端接结构和用台面端接结构形成功率半导体器件的方法

    公开(公告)号：US08460977B2

    公开(公告)日：2013-06-11

    申请号：US13338620

    申请日：2011-12-28

    申请人： Qingchun Zhang ,  Anant K. Agarwal

    发明人： Qingchun Zhang ,  Anant K. Agarwal

    IPC分类号： H01L21/335

    CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/744 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/8613

    摘要： A method of forming an electronic device, including forming a preliminary buffer layer on a drift layer, forming a first layer on the preliminary buffer layer, selectively etching the first layer to form a first mesa that exposes a portion of the preliminary buffer layer, and selectively etching the exposed portion of the preliminary buffer layer to form a second mesa that covers a first portion of the drift layer, that exposes a second portion of the drift layer, and that includes a mesa step that protrudes from the first mesa. Dopants are selectively implanted into the drift layer adjacent the second mesa to form a junction termination region in the drift layer. Dopants are selectively implanted through a horizontal surface of the mesa step into a portion of the drift layer beneath the mesa step to form a buried junction extension in the drift layer.

    摘要翻译： 一种形成电子器件的方法，包括在漂移层上形成初步缓冲层，在预备缓冲层上形成第一层，选择性地蚀刻第一层以形成露出一部分初步缓冲层的第一台面;以及 选择性地蚀刻初步缓冲层的暴露部分以形成覆盖漂移层的第一部分的第二台面，其暴露漂移层的第二部分，并且包括从第一台面突出的台面台阶。 将掺杂剂选择性地注入到与第二台面相邻的漂移层中以在漂移层中形成结终止区域。 选择性地将掺杂剂通过台面台阶的水平表面植入台阶下面的漂移层的一部分，以在漂移层中形成掩埋结延伸。

    Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same
    10.
    发明授权
    Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same 有权
    包括具有排列成岛的掺杂区域的肖特基二极管的半导体器件及其制造方法

    公开(公告)号：US08330244B2

    公开(公告)日：2012-12-11

    申请号：US12492670

    申请日：2009-06-26

    申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

    CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

    摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

    摘要翻译： 根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。 多个间隔开的第一掺杂区域被布置在有源区域内。 多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。 多个第一掺杂区域在半导体层中被布置为岛状。 半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。