公开(公告)号：US06849510B2

公开(公告)日：2005-02-01

申请号：US10667919

申请日：2003-09-22

申请人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

发明人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823864 ,  H01L21/823878

摘要： Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

摘要翻译： 用于制造半导体器件（例如MOSFET器件）的非氧化间隔物致密化方法，并且可以在半导体制造期间实施，在间隔物致密化期间几乎没有或基本上没有聚硅氧烷粘附损失。 该方法可以实现以通过消除对附加工艺步骤（例如金属硅化物封装或多晶硅表面处理）的需要来提供优于常规方法的降低的工艺复杂性的良好的多晶硅化合物附着特性。

公开(公告)号：US06642112B1

公开(公告)日：2003-11-04

申请号：US09918364

申请日：2001-07-30

申请人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

发明人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

IPC分类号： H01L218234

CPC分类号： H01L21/823842 ,  H01L21/823864 ,  H01L21/823878

摘要： Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

摘要翻译： 用于制造半导体器件（例如MOSFET器件）的非氧化间隔物致密化方法，并且可以在半导体制造期间实施，在间隔物致密化期间几乎没有或基本上没有聚硅氧烷粘附损失。 该方法可以实现以通过消除对附加工艺步骤（例如金属硅化物封装或多晶硅表面处理）的需要来提供优于常规方法的降低的工艺复杂性的良好的多晶硅化合物附着特性。

公开(公告)号：US6165846A

公开(公告)日：2000-12-26

申请号：US260913

申请日：1999-03-02

申请人： Timothy K. Carns ,  John A. Smythe, III ,  John A. Ransom ,  Bernice L. Kickel ,  John E. Berg

发明人： Timothy K. Carns ,  John A. Smythe, III ,  John A. Ransom ,  Bernice L. Kickel ,  John E. Berg

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/518

摘要： The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.

摘要翻译： 用于EEPROM和FLASH技术的薄隧道氧化物的改进使用氮中的后氧化退火在随后的氧化膜中引起缺陷。 这些表现为鸟喙处的氧化物变薄，导致高漏电。 随着后氧化退火的时间和温度增加，隧道氧化物性能的提高，缺陷数量迅速增加。 示出了使用更高的后氧化时间和温度退火实现改进的隧道氧化物QBD的方法，同时不降低随后的栅极氧化物的质量。 描述了在晶体管栅极氧化之前使用牺牲氧化和条带。 该工艺除去存在于场边缘的附加氮化物，导致氧化物变薄。 结果，可以在不降低高压和低压晶体管的情况下实现改进的隧道氧化物完整性。

公开(公告)号：US08017475B1

公开(公告)日：2011-09-13

申请号：US12804414

申请日：2010-07-20

申请人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

发明人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

IPC分类号： H01L21/8242

CPC分类号： H01L28/57 ,  H01L27/0629 ,  H01L27/0805

摘要： A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer that is later etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

摘要翻译： 描述了可以并入适用于亚微米器件的标准CMOS制造工艺中的制造高性能电容器的方法。 可以保持在标准CMOS工艺中使用的参数，特别是对于下电极层的定义和蚀刻。 为了减小临界尺寸宽度的变化，使用抗反射层（ARL），例如等离子体增强化学气相沉积抗反射层（PEARL）或其它抗反射涂层（ARCS），例如导电膜 锡。 该ARL形成发生在电容器特定工艺步骤之后，但在用于限定下电极的掩模之前。 在从电容器区域外的晶体管多晶硅去除不需要的电容器介电层之后，但在PEARL沉积之前，执行快速热氧化（RTO）。 另一个实施例代替消除了电容器介质去除步骤，然后由步骤代替以形成附加层，随后蚀刻掉附加层以在电容器侧留下间隔物，从而消除电介质的任何底切。

公开(公告)号：US08324069B1

公开(公告)日：2012-12-04

申请号：US13134159

申请日：2011-05-31

申请人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

发明人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

IPC分类号： H01L21/20

CPC分类号： H01L28/57 ,  H01L27/0629 ,  H01L27/0805

摘要： A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer that is later etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

摘要翻译： 描述了可以并入适用于亚微米器件的标准CMOS制造工艺中的制造高性能电容器的方法。 可以保持在标准CMOS工艺中使用的参数，特别是对于下电极层的定义和蚀刻。 为了减小临界尺寸宽度的变化，使用抗反射层（ARL），例如等离子体增强化学气相沉积抗反射层（PEARL）或其它抗反射涂层（ARCS），例如导电膜 锡。 该ARL形成发生在电容器特定工艺步骤之后，但在用于限定下电极的掩模之前。 在从电容器区域外的晶体管多晶硅去除不需要的电容器介电层之后，但在PEARL沉积之前，执行快速热氧化（RTO）。 另一个实施例代替消除了电容器介质去除步骤，然后由步骤代替以形成附加层，随后蚀刻掉附加层以在电容器侧留下间隔物，从而消除电介质的任何底切。

公开(公告)号：US07768052B1

公开(公告)日：2010-08-03

申请号：US11289262

申请日：2005-11-29

申请人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

发明人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L28/57 ,  H01L27/0629 ,  H01L27/0805

摘要： A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer that is later etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

摘要翻译： 描述了可以并入适用于亚微米器件的标准CMOS制造工艺中的制造高性能电容器的方法。 可以保持在标准CMOS工艺中使用的参数，特别是对于下电极层的定义和蚀刻。 为了减小临界尺寸宽度的变化，使用抗反射层（ARL），例如等离子体增强化学气相沉积抗反射层（PEARL）或其它抗反射涂层（ARCS），例如导电膜 锡。 该ARL形成发生在电容器特定工艺步骤之后，但在用于限定下电极的掩模之前。 在从电容器区域外的晶体管多晶硅去除不需要的电容器介电层之后，但在PEARL沉积之前，执行快速热氧化（RTO）。 另一个实施例代替消除电容器电介质去除步骤，然后由步骤代替以形成附加层，该附加层随后被蚀刻掉以在电容器侧留下间隔物，由此消除电介质的任何底切。

公开(公告)号：US06323091B1

公开(公告)日：2001-11-27

申请号：US09354884

申请日：1999-07-16

申请人： Sungkwon Lee ,  Timothy K. Carns

发明人： Sungkwon Lee ,  Timothy K. Carns

IPC分类号： H01L218234

CPC分类号： H01L27/11293 ,  H01L21/823814 ,  H01L27/105

摘要： A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditions as the MOS transistor forming step. Only a single mask needs to be modified for the programming, thus reducing cost and complexity of manufacturing the device.

摘要翻译： 一种制造半导体器件的方法，其中通过利用与用于在MOS晶体管中注入掺杂剂所用的掩模相同的掩模来执行ROM编程离子注入。 ROM编程离子注入在与MOS晶体管形成步骤相同的条件下进行。 需要对编程进行修改，从而降低了制造设备的成本和复杂性。

公开(公告)号：US5684737A

公开(公告)日：1997-11-04

申请号：US569848

申请日：1995-12-08

申请人： Kang L. Wang ,  Xinyu Zheng ,  Timothy K. Carns

发明人： Kang L. Wang ,  Xinyu Zheng ,  Timothy K. Carns

IPC分类号： G11C11/36 ,  H01L27/11 ,  H01L29/88 ,  G11C11/34 ,  H01L29/06

CPC分类号： H01L29/882 ,  G11C11/36 ,  H01L27/11 ,  Y10S257/903

摘要： A static random access memory (SRAM) cell includes a bistable diode and a load device serially connectable between two voltage potentials (VDD, Ground) with a gate device (field effect transistor) connected between a bit line and a common terminal of the bistable diode and load device and a control terminal of the gate device connected to a word line. The bistable diode includes a GeSi structure between a p-doped semiconductor region and a spaced n-doped semiconductor region. The GeSi structure can be a GeSi/Si superlattice and a .delta.-doped tunnel junction, a Ge.sub.x Si.sub.1-x multiple well structure, or a .delta.-doped tunnel junction.

摘要翻译： 静态随机存取存储器（SRAM）单元包括双稳态二极管和可连接在两个电压电位（VDD，Ground）之间的负载装置与连接在双向稳定二极管的位线和公共端之间的栅极器件（场效应晶体管） 和负载装置以及连接到字线的栅极装置的控制端子。 双稳态二极管包括在p掺杂半导体区域和间隔开的n掺杂半导体区域之间的GeSi结构。 GeSi结构可以是GeSi / Si超晶格和δ-掺杂的隧道结，GexSi1-x多阱结构或δ-掺杂隧道结。

公开(公告)号：US07060584B1

公开(公告)日：2006-06-13

申请号：US09351544

申请日：1999-07-12

申请人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

发明人： Timothy K. Carns ,  John L. Horvath ,  Lee J. DeBruler ,  Michael J. Westphal

IPC分类号： H01L21/331

CPC分类号： H01L28/57 ,  H01L27/0629 ,  H01L27/0805

摘要： A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used. In the preferred embodiment, this is of the Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) type, although other Anti-Reflective Coatings (ARCs) or layers, such as a conductive film like TiN may be employed. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. In one embodiment, a Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer which, in a second step, is then etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

摘要翻译： 描述了一种制造可以并入适用于亚微米器件的标准CMOS制造工艺中的高性能电容器的方法。 可以保持在标准CMOS工艺中使用的参数，特别是对于下电极层的定义和蚀刻。 为了减小关键尺寸宽度的变化，使用抗反射层（ARL）。 在优选实施例中，这是等离子体增强化学气相沉积抗反射层（PEARL）型，但是也可以使用其它抗反射涂层（ARC）或诸如TiN等导电膜的层。 该ARL形成发生在电容器特定工艺步骤之后，但在用于限定下电极的掩模之前。 在一个实施例中，在从电容器区域外的晶体管多晶硅聚集层除去不想要的电容器介电层之前，但在PEARL沉积之前，执行快速热氧化（RTO）。 另一实施例代替消除了电容器电介质去除步骤，然后由步骤代替以形成附加层，然后在第二步中蚀刻掉附加层，以在电容器侧留下间隔物，从而消除电介质的任何底切。

公开(公告)号：US5965931A

公开(公告)日：1999-10-12

申请号：US306795

申请日：1994-09-15

申请人： Kang L. Wang ,  Timothy K. Carns ,  Xinyu Zheng

发明人： Kang L. Wang ,  Timothy K. Carns ,  Xinyu Zheng

IPC分类号： H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/7371 ,  H01L29/7373

摘要： A bipolar transistor includes multiple coupled delta layers in the base region between the emitter and collector regions to enhance carrier mobility and conductance. The delta layers can be varied in number, thickness, and dopant concentration to optimize desired device performance and enhanced mobility and conductivity vertically for emitter to collector and laterally parallel to the delta-doped layers. The transistors can be homojunction devices or heterojunction devices formed in either silicon or III-V semiconductor material.

摘要翻译： 双极晶体管包括在发射极和集电极区域之间的基极区域中的多个耦合的三角形层，以增强载流子迁移率和电导率。 三角形层可以在数量，厚度和掺杂剂浓度上变化，以优化所需的器件性能，并且对于发射极到集电极垂直地提高迁移率和导电性，并且横向平行于δ-掺杂层。 晶体管可以是在硅或III-V半导体材料中形成的同相结合器件或异质结器件。