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    High speed data link with transmitter equalization and receiver equalization
    1.
    发明申请
    High speed data link with transmitter equalization and receiver equalization 有权
    具有发射机均衡和接收机均衡的高速数据链路

    公开(公告)号：US20040071219A1

    公开(公告)日：2004-04-15

    申请号：US10680490

    申请日：2003-10-08

    Applicant: Broadcom Corporation

    Inventor： Pieter Vorenkamp ,  Aaron Buchwald

    IPC: H04B003/00 ,  H04L025/00

    CPC classification number: H04L25/03878 ,  H04B3/144

    Abstract: A high speed data link includes transmitter equalization and (passive) receiver equalization to compensate for frequency distortion of the data link. In one embodiment, the transmitter equalization is performed with a de-emphasis circuit. The transmitter de-emphasis circuit pre-distorts an input signal to compensate for at least some of the frequency distortion in the data caused by the transmission line. The (passive) receive equalization circuit further compensates for the frequency distortion at the output of the transmission line to flatten the amplitude response of the output signal, and thereby reduce inter-symbol interference, improve media reach and improve the bit error rate (BER).

    Abstract translation: 高速数据链路包括发射机均衡和（无源）接收机均衡以补偿数据链路的频率失真。 在一个实施例中，用去加重电路来执行发射机均衡。 发射机去加重电路预失真输入信号以补偿由传输线引起的数据中的至少一些频率失真。 （无源）接收均衡电路进一步补偿传输线输出端的频率失真，使输出信号的振幅响应平坦化，从而减少符号间干扰，提高媒体距离，提高误码率（BER） 。

    Variable gain amplifier for low voltage applications
    2.
    发明申请
    Variable gain amplifier for low voltage applications 有权
    用于低电压应用的可变增益放大器

    公开(公告)号：US20040219898A1

    公开(公告)日：2004-11-04

    申请号：US10747124

    申请日：2003-12-30

    Applicant: Broadcom Corporation

    Inventor： Klaas Bult ,  Rudy Van De Plassche ,  Pieter Vorenkamp ,  Arnoldus Venes

    IPC: H04B007/00

    CPC classification number: H03G3/30 ,  H03F1/34 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45644 ,  H03G1/0029 ,  H04B2001/0433

    Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

    Abstract translation: 综合通信系统。 包括具有设置在基板上的接收器的基板，用于将接收信号转换成IF信号。 耦合到VGA用于低电压应用并耦合到接收机处理IF信号。 VGA包括具有第一组差分晶体管组和第二组差分晶体管组的存储体对。 银行对并行交叉耦合，IF信号被施加到从用于在一定范围的输入电压上控制存储体对的跨导输出增益的控制信号去耦的存储体对。 数字IF解调器设置在衬底上并耦合到用于低电压应用的VGA，用于将IF信号转换成解调的基带信号。 并且发射机设置在与接收器协作操作的基板上以建立双向通信路径。

    Applications for differential cystal oscillator
    3.
    发明申请
    Applications for differential cystal oscillator 有权
    差分晶体振荡器的应用

    公开(公告)号：US20040160286A1

    公开(公告)日：2004-08-19

    申请号：US10783563

    申请日：2004-02-23

    Applicant: Broadcom Corporation

    Inventor： Christopher M. Ward ,  Pieter Vorenkamp

    IPC: H04N009/77

    CPC classification number: H03J3/185 ,  H01F17/0006 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L27/08 ,  H03B5/364 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J2200/10

    Abstract: A periodic signal generation circuit includes a differential crystal oscillator suitable for integration on a semiconductor substrate. The oscillator utilizes an external crystal as a resonator. The circuit is designed such that differential sinusoidal signals are present on the resonator leads to provide superior noise rejection of interfering signals. Differential signal transmission is maintained throughout the oscillator to reject noise generated by other circuitry that may be present on the substrate. Noise radiated out from the oscillator through the power supply, substrate, bond wires and pads is reduced due to the generation of differential signals of controlled sinusoidal amplitude and low harmonic content. The oscillator produces low phase noise so that the oscillator may be used in applications, such as TV receivers, that are sensitive to distortion. The circuit is a square wave that has low jitter, thus reducing jitter produced in digital circuits that, would utilize this square wave clock signal.

    Abstract translation: 周期性信号发生电路包括适于集成在半导体衬底上的差分晶体振荡器。 振荡器利用外部晶体作为谐振器。 电路被设计成使得谐振器引线上存在差分正弦信号以提供干扰信号的优异的噪声抑制。 在整个振荡器中保持差分信号传输以抑制由衬底上可能存在的其它电路产生的噪声。 由于产生了受控正弦波幅度和低谐波含量的差分信号，因此通过电源，基板，接合线和焊盘从振荡器辐射的噪声被减小。 振荡器产生低相位噪声，使振荡器可用于对失真敏感的应用中，如电视接收机。 该电路是具有低抖动的方波，从而减少数字电路产生的抖动，这将会利用该方波时钟信号。

    Reference ladder having improved feedback stability
    4.
    发明申请
    Reference ladder having improved feedback stability 有权
    参考梯具有改进的反馈稳定性

    公开(公告)号：US20030231051A1

    公开(公告)日：2003-12-18

    申请号：US10283088

    申请日：2002-10-30

    Applicant: Broadcom Corporation

    Inventor： Pieter Vorenkamp

    IPC: G05F001/10

    CPC classification number: H03M1/0602 ,  H03M1/365

    Abstract: A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks. An alternate embodiment includes first and second resistor ladders that are configured to generate substantially identical voltages across their respective taps. First and second feedback networks sense voltages on the first resistor ladder and control current sources that drive both the first resistor ladder and the second resistor ladder. Differential input stages that are connected to the taps of the second resistor ladder and are at least partially isolated from the feedback networks that are connected to the first resistor ladder, thereby improving stability of the feedback networks.

    Abstract translation: 参考梯形图被配置为具有改进的反馈稳定性。 参考梯形电路包括具有产生多个参考电压的多个抽头的电阻梯。 电阻梯由多个抽头中的第一抽头的第一电流源和多个抽头的第二抽头处的第二电流源驱动。 第一反馈网络感测在第一抽头处的电压，并且基于第一感测电压来控制第一电流源。 第二反馈网络感测第二抽头处的电压，并且基于第二感测电压来控制第二电流源。 第一和第二抽头各自用作电阻梯的力抽头和感测抽头。 通过收敛力和感测抽头，连接到多个抽头的差分输入级至少部分地与反馈网络隔离，从而提高反馈网络的稳定性。 替代实施例包括被配置为在它们各自的抽头上产生基本上相同的电压的第一和第二电阻器梯形。 第一和第二反馈网络检测第一电阻梯的电压和驱动第一电阻梯和第二电阻梯的控制电流源。 差分输入级连接到第二电阻梯的抽头并且至少部分地与连接到第一电阻梯的反馈网络隔离，从而提高反馈网络的稳定性。

    Slew rate controlled output buffer
    6.
    发明申请
    Slew rate controlled output buffer 有权
    压摆率控制输出缓冲器

    公开(公告)号：US20040207452A1

    公开(公告)日：2004-10-21

    申请号：US10413519

    申请日：2003-04-15

    Applicant: Broadcom Corporation

    Inventor： Pieter Vorenkamp

    IPC: H03K017/16 ,  H03K017/30

    CPC classification number: H03K19/00361

    Abstract: An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

    Abstract translation: 输出缓冲器包括耦合在输入和输出端子之间的第一和第二电路部分。 每个电路部分包括电容元件; 具有耦合到所述电容元件的栅极的输出晶体管和驱动所述输出端子处的电压的漏极; 以及电流发生器，其被配置为响应于所述输入端子处的逻辑转换而产生针对所述电容元件的充电电流，其中所述充电电流在所述输出晶体管的栅极处形成基本线性的斜坡电压，由此所述斜坡 电压控制输出端电压的转换速率。

    Frequency division/multiplication with jitter minimization
    8.
    发明申请
    Frequency division/multiplication with jitter minimization 有权
    分频/乘法与抖动最小化

    公开(公告)号：US20040169534A1

    公开(公告)日：2004-09-02

    申请号：US10782890

    申请日：2004-02-23

    Applicant: Broadcom Corporation

    Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

    IPC: H03L007/06

    CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

    Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

    Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

    Frequency division/multiplication with jitter minimization
    9.
    发明申请
    Frequency division/multiplication with jitter minimization 有权
    分频/乘法与抖动最小化

    公开(公告)号：US20030058009A1

    公开(公告)日：2003-03-27

    申请号：US10227259

    申请日：2002-08-26

    Applicant: Broadcom Corporation

    Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

    IPC: H03K021/00

    CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

    Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

    Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

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