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1.发明申请公开(公告)号：US20100081232A1
公开(公告)日：2010-04-01
申请号：US12544226
申请日：2009-08-20
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L21/768 , H01L21/2007 , H01L21/84 , H01L23/3735 , H01L27/0688 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.
摘要翻译： 提供了一种用于半导体部件的结构，其具有通过其它有源，无源和互连部件夹在两侧的器件层。 使用晶片级层传输过程来创建具有附加功能增强的平面（2D）IC结构。
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2.发明授权Layer transfer process and functionally enhanced integrated circuits produced thereby 有权层转移过程和由此产生的功能增强的集成电路公开(公告)号：US07855101B2
公开(公告)日：2010-12-21
申请号：US12544226
申请日：2009-08-20
IPC分类号： H01L21/50
CPC分类号： H01L21/768 , H01L21/2007 , H01L21/84 , H01L23/3735 , H01L27/0688 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.
摘要翻译： 提供了一种用于半导体部件的结构，其具有通过其它有源，无源和互连部件夹在两侧的器件层。 使用晶片级层传输过程来创建具有附加功能增强的平面（2D）IC结构。
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3.发明申请Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby 审中-公开层传输过程和功能强化的集成电路产品公开(公告)号：US20080277778A1
公开(公告)日：2008-11-13
申请号：US11746680
申请日：2007-05-10
CPC分类号： H01L21/768 , H01L21/2007 , H01L21/84 , H01L23/3735 , H01L27/0688 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.
摘要翻译： 提供了一种用于半导体部件的结构，其具有通过其它有源，无源和互连部件夹在两侧的器件层。 使用晶片级层传输过程来创建具有附加功能增强的平面（2D）IC结构。
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4.发明授权Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair 失效处理等离子体损伤层进行临界尺寸保留，孔密封和修复公开(公告)号：US07750479B2
公开(公告)日：2010-07-06
申请号：US11857797
申请日：2007-09-19
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of fabricating the same in which the critical dimension of the conductive features are not altered by a plasma damaged layer are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modifies the density of the dielectric material such that the treated surfaces become denser than the bulk dielectric not subjected to the treatment. The treatment step is performed prior to deposition of the noble metal liner.
摘要翻译： 提供一种互连结构及其制造方法，其中导电特征的临界尺寸不被等离子体损伤层改变。 根据本发明，对化学蚀刻介电材料进行处理步骤，该处理步骤改变介电材料的密度，使得处理的表面变得比不经受处理的体电介质更致密。 处理步骤在沉积贵金属衬垫之前进行。
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公开(公告)号：US20090075472A1
公开(公告)日：2009-03-19
申请号：US11857760
申请日：2007-09-19
申请人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
发明人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.
摘要翻译： 提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。 等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。 以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽 用于形成线沟槽和通孔腔的离子蚀刻。 减少的线偏压对金属互连结构的电产量具有有益的影响。
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6.发明申请TREATMENT OF PLASMA DAMAGED LAYER FOR CRITICAL DIMENSION RETENTION, PORE SEALING AND REPAIR 失效等离子体损伤层的处理用于关键尺寸保持，孔密封和修复公开(公告)号：US20080042283A1
公开(公告)日：2008-02-21
申请号：US11857797
申请日：2007-09-19
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of fabricating the same in which the critical dimension of the conductive features are not altered by a plasma damaged layer are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modifies the density of the dielectric material such that the treated surfaces become denser than the bulk dielectric not subjected to the treatment. The treatment step is performed prior to deposition of the noble metal liner.
摘要翻译： 提供了一种互连结构及其制造方法，其中导电特征的临界尺寸不被等离子体损伤层改变。 根据本发明，对化学蚀刻介电材料进行处理步骤，该处理步骤改变介电材料的密度，使得处理的表面变得比不经受处理的体电介质更致密。 处理步骤在沉积贵金属衬垫之前进行。
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公开(公告)号：US07830010B2
公开(公告)日：2010-11-09
申请号：US12062130
申请日：2008-04-03
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76849 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O.
摘要翻译： 提供了其中含有贵金属的覆盖层直接存在于嵌入低k电介质材料的导电材料的非凹陷表面上的互连结构。 已经确定，在金属盖形成之前通过在低k电介质材料上形成疏水表面提供了一种用于直接控制在导电材料的非凹入表面上选择性形成金属帽的手段。 也就是说，直接在导电材料的非凹入表面上选择性地形成金属帽，因为金属帽在导电材料的非凹陷表面上的形成速率大于导电材料的疏水表面上的形成速率 低k电介质材料。 观察到，疏水性表面可以是在选择性形成贵金属盖之前用甲硅烷基化剂处理电介质材料的损坏表面的结果，或者由于在表面上形成疏水性聚合物层 在贵金属盖的选择性沉积之前的介电材料。 疏水性聚合物层通常包括Si，C和O的原子。
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公开(公告)号：US20090250815A1
公开(公告)日：2009-10-08
申请号：US12062130
申请日：2008-04-03
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76849 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O.
摘要翻译： 提供了其中含有贵金属的覆盖层直接存在于嵌入低k电介质材料的导电材料的非凹陷表面上的互连结构。 已经确定，在金属盖形成之前通过在低k电介质材料上形成疏水表面提供了一种用于直接控制在导电材料的非凹入表面上选择性形成金属帽的手段。 也就是说，直接在导电材料的非凹入表面上选择性地形成金属帽，因为金属帽在导电材料的非凹陷表面上的形成速率大于导电材料的疏水表面上的形成速率 低k电介质材料。 观察到，疏水性表面可以是在选择性形成贵金属盖之前用甲硅烷基化剂处理电介质材料的损坏表面的结果，或者由于在表面上形成疏水性聚合物层 在贵金属盖的选择性沉积之前的介电材料。 疏水性聚合物层通常包括Si，C和O的原子。
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9.发明申请METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER 失效使用保护性顶板间隔器减少有机硅电极中的等离子体损伤的方法公开(公告)号：US20090072401A1
公开(公告)日：2009-03-19
申请号：US11857805
申请日：2007-09-19
申请人： John C. Arnold , Sampath Purushothaman , Muthumanickam Sankarapandian , Hosadurga K. Shobha , Terry A. Spooner
发明人： John C. Arnold , Sampath Purushothaman , Muthumanickam Sankarapandian , Hosadurga K. Shobha , Terry A. Spooner
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.
摘要翻译： 在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。 致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。 保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。
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公开(公告)号：US08481423B2
公开(公告)日：2013-07-09
申请号：US11857760
申请日：2007-09-19
申请人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
发明人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.
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