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239 条记录 (耗时 0.026 秒)

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20100309741A1

    公开(公告)日：2010-12-09

    申请号：US12859445

    申请日：2010-08-19

    申请人： HIROYUKI MIZUNO ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

    发明人： HIROYUKI MIZUNO ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

    摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

    摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。 读出放大器SA包括第一电路，其包括具有连接到位线BL的栅极的差分MOS对，以及连接到用于全幅放大的局部位线LBL并用于保持该数据的第二电路。 当位线BL和本地位线LBL通过电容器电容耦合时，建议使用连接到局部位线LBL的锁存型读出放大器SA。

    Semiconductor device with level converter having signal-level shifting block and signal-level determination block
    8.
    发明申请
    Semiconductor device with level converter having signal-level shifting block and signal-level determination block 有权

    公开(公告)号：US20060197579A1

    公开(公告)日：2006-09-07

    申请号：US11410956

    申请日：2006-04-26

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0016 ,  H03K19/018521

    摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

    Semiconductor device
    9.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20050190612A1

    公开(公告)日：2005-09-01

    申请号：US11117479

    申请日：2005-04-29

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    IPC分类号： G11C5/00 ,  H03K19/0185

    CPC分类号： H03K19/0016 ,  H03K19/018521

    摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

    摘要翻译： 公开了一种包括电平转换器（LSC）的半导体器件。 电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2） 电源（VDDQ）。 升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。 该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。 为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC） 自动控制防泄漏，外接控制信号。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US06933765B2

    公开(公告)日：2005-08-23

    申请号：US10149189

    申请日：2000-12-21

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

    IPC分类号： G11C5/00 ,  H03K19/0185 ,  H03L5/00

    CPC分类号： H03K19/0016 ,  H03K19/018521

    摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.