Semiconductor structure
    2.
    发明授权

    公开(公告)号:US11984369B2

    公开(公告)日:2024-05-14

    申请号:US17373948

    申请日:2021-07-13

    发明人: ChihCheng Liu

    IPC分类号: H01L21/66 H01L27/092

    CPC分类号: H01L22/32 H01L27/092

    摘要: A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor.

    On die termination circuit and memory device

    公开(公告)号:US11888474B2

    公开(公告)日:2024-01-30

    申请号:US17385439

    申请日:2021-07-26

    发明人: ChihCheng Liu

    IPC分类号: H03K19/00 G11C7/10

    摘要: An on die termination (ODT) circuit includes a signal input terminal; a grounding terminal; a first transistor including a control terminal and a first terminal which are electrically connected with the signal input terminal, and a second terminal electrically connected with the grounding terminal; and a second transistor including a control terminal electrically connected with the signal input terminal, a first terminal, and a second terminal electrically connected with the grounding terminal, and when voltage of the signal input terminal changes, the first transistor has a change trend of resistance opposite to that of the second transistor.

    Active region array formation method

    公开(公告)号:US12100594B2

    公开(公告)日:2024-09-24

    申请号:US17595589

    申请日:2021-03-12

    发明人: ChihCheng Liu

    摘要: An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.

    Semiconductor device with a doped well region

    公开(公告)号:US11894363B2

    公开(公告)日:2024-02-06

    申请号:US17443505

    申请日:2021-07-27

    发明人: ChihCheng Liu

    IPC分类号: H01L27/02 H01L29/74

    CPC分类号: H01L27/0262 H01L29/7436

    摘要: A semiconductor device includes: a doped well region of a first conductive type; M semiconductor components, the M semiconductor components being provided in the doped well region of the first conductive type and being arranged in the doped well region of the first conductive type in a first direction, M being a positive integer, each semiconductor component including a first doped region of a second conductive type and a doped region of a first conductive type, and the doped region of the first conductive type surrounding the first doped region of the second conductive type; and second doped regions of a second conductive type, the second doped regions of the second conductive type being provided on at least one side of the M semiconductor components in the first direction.

    Anti-fuse unit and anti-fuse array

    公开(公告)号:US11869608B2

    公开(公告)日:2024-01-09

    申请号:US17384945

    申请日:2021-07-26

    发明人: ChihCheng Liu

    IPC分类号: G11C17/16 H01L23/525

    CPC分类号: G11C17/16 H01L23/5252

    摘要: An anti-fuse unit and an anti-fuse array. The anti-fuse unit includes an anti-fuse device and a diode. An anode of the anti-fuse device is electrically connected with a bit line, a cathode of the anti-fuse device is electrically connected with an anode of the diode, and a cathode of the diode is electrically connected with a word line.

    Memory and method for manufacturing same

    公开(公告)号:US11864375B2

    公开(公告)日:2024-01-02

    申请号:US17372893

    申请日:2021-07-12

    发明人: ChihCheng Liu

    IPC分类号: H10B12/00 H01L29/06

    摘要: A memory and a method for manufacturing the same are provided. The memory includes: a substrate including an isolation structure and an active area between adjacent isolation structures; a first gate structure, the first gate structure locates in a first groove of the isolation structure, includes a first gate filled in the first groove, and the first gate includes a first conductive layer filled at the bottom of the first groove and a second conductive layer, the second conductive layer locates above the first conductive layer, and the work function of the material of the first conductive layer is greater than that of the material of the second conductive layer; a second gate structure, located in the second groove of the active area, includes a second gate filled in the second groove, and the material of the second gate is the same as that of the second conductive layer.

    WORD LINE LEAD-OUT STRUCTURE AND METHOD FOR PREPARING SAME

    公开(公告)号:US20210375329A1

    公开(公告)日:2021-12-02

    申请号:US17400456

    申请日:2021-08-12

    发明人: ChihCheng Liu

    IPC分类号: G11C5/06 G11C5/02

    摘要: The present application relates to a word line lead-out structure and a method for preparing the same. A word line extending along an X-axis direction is formed on a substrate. A contact hole covering the word line along a Y-axis direction is formed, the X-axis direction being perpendicular to the Y-axis direction. A metal line covering the contact hole is formed, the contact hole being located between the word line and the metal line and being contacted with the word line and the metal line. The contact area between the contact hole and the metal line is larger than that between the contact hole and the word line.