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公开(公告)号：US12119286B2
公开(公告)日：2024-10-15
申请号：US17647883
申请日：2022-01-13
发明人： ChihCheng Liu
IPC分类号： H01L21/00 , H01L21/768 , H01L23/48 , H01L23/528 , H01L23/532 , H01L25/065
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5283 , H01L23/53228 , H01L23/53257 , H01L25/0657 , H01L2225/06541
摘要： A die, a memory and a method of manufacturing the die are provided. The die includes a substrate and a conductive structure, where the substrate has an interconnection structure layer, the conductive structure includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, and a coefficient of thermal expansion of the first conductive structure is smaller than that of copper.
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公开(公告)号：US11984369B2
公开(公告)日：2024-05-14
申请号：US17373948
申请日：2021-07-13
发明人： ChihCheng Liu
IPC分类号： H01L21/66 , H01L27/092
CPC分类号： H01L22/32 , H01L27/092
摘要： A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor.
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公开(公告)号：US11888474B2
公开(公告)日：2024-01-30
申请号：US17385439
申请日：2021-07-26
发明人： ChihCheng Liu
CPC分类号： H03K19/0005 , G11C7/1048 , G11C7/1051
摘要： An on die termination (ODT) circuit includes a signal input terminal; a grounding terminal; a first transistor including a control terminal and a first terminal which are electrically connected with the signal input terminal, and a second terminal electrically connected with the grounding terminal; and a second transistor including a control terminal electrically connected with the signal input terminal, a first terminal, and a second terminal electrically connected with the grounding terminal, and when voltage of the signal input terminal changes, the first transistor has a change trend of resistance opposite to that of the second transistor.
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公开(公告)号：US12100594B2
公开(公告)日：2024-09-24
申请号：US17595589
申请日：2021-03-12
发明人： ChihCheng Liu
IPC分类号： H01L21/033 , H01L21/265 , H01L21/266 , H10B12/00
CPC分类号： H01L21/0338 , H01L21/0335 , H01L21/0337 , H01L21/26513 , H01L21/266 , H10B12/00
摘要： An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.
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公开(公告)号：US11894363B2
公开(公告)日：2024-02-06
申请号：US17443505
申请日：2021-07-27
发明人： ChihCheng Liu
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A semiconductor device includes: a doped well region of a first conductive type; M semiconductor components, the M semiconductor components being provided in the doped well region of the first conductive type and being arranged in the doped well region of the first conductive type in a first direction, M being a positive integer, each semiconductor component including a first doped region of a second conductive type and a doped region of a first conductive type, and the doped region of the first conductive type surrounding the first doped region of the second conductive type; and second doped regions of a second conductive type, the second doped regions of the second conductive type being provided on at least one side of the M semiconductor components in the first direction.
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公开(公告)号：US11869608B2
公开(公告)日：2024-01-09
申请号：US17384945
申请日：2021-07-26
发明人： ChihCheng Liu
IPC分类号： G11C17/16 , H01L23/525
CPC分类号： G11C17/16 , H01L23/5252
摘要： An anti-fuse unit and an anti-fuse array. The anti-fuse unit includes an anti-fuse device and a diode. An anode of the anti-fuse device is electrically connected with a bit line, a cathode of the anti-fuse device is electrically connected with an anode of the diode, and a cathode of the diode is electrically connected with a word line.
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公开(公告)号：US11864375B2
公开(公告)日：2024-01-02
申请号：US17372893
申请日：2021-07-12
发明人： ChihCheng Liu
CPC分类号： H10B12/34 , H01L29/0649 , H10B12/053
摘要： A memory and a method for manufacturing the same are provided. The memory includes: a substrate including an isolation structure and an active area between adjacent isolation structures; a first gate structure, the first gate structure locates in a first groove of the isolation structure, includes a first gate filled in the first groove, and the first gate includes a first conductive layer filled at the bottom of the first groove and a second conductive layer, the second conductive layer locates above the first conductive layer, and the work function of the material of the first conductive layer is greater than that of the material of the second conductive layer; a second gate structure, located in the second groove of the active area, includes a second gate filled in the second groove, and the material of the second gate is the same as that of the second conductive layer.
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公开(公告)号：US20210375329A1
公开(公告)日：2021-12-02
申请号：US17400456
申请日：2021-08-12
发明人： ChihCheng Liu
摘要： The present application relates to a word line lead-out structure and a method for preparing the same. A word line extending along an X-axis direction is formed on a substrate. A contact hole covering the word line along a Y-axis direction is formed, the X-axis direction being perpendicular to the Y-axis direction. A metal line covering the contact hole is formed, the contact hole being located between the word line and the metal line and being contacted with the word line and the metal line. The contact area between the contact hole and the metal line is larger than that between the contact hole and the word line.
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公开(公告)号：US12062610B2
公开(公告)日：2024-08-13
申请号：US17400562
申请日：2021-08-12
发明人： ChihCheng Liu
IPC分类号： H01L23/528 , H01L21/311 , H01L21/768 , H10B10/00 , H10B12/00 , H10B20/00 , H10B41/40 , H10B43/40 , H10B51/40 , H10B53/40
CPC分类号： H01L23/5283 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H10B10/18 , H10B12/50 , H10B20/60 , H10B41/40 , H10B43/40 , H10B51/40 , H10B53/40
摘要： A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes following operations. A semiconductor substrate is provided. The semiconductor substrate includes an array region and a peripheral region, a plurality of conductive layers are arranged in array region and separated from each other. A support layer covering the semiconductor substrate is formed. An interconnect layer is arranged in support layer located on the array region and extends to peripheral region. The interconnect layer is electrically connected to a respective one of the conductive layers and transmits an electrical signal of the respective one of the conductive layers to the peripheral region. The support layer is patterned to form a plurality of support structures located on the peripheral region and separated from each other and an interconnect structure located on the array region and peripheral region. The interconnect layer is located in the interconnect structure.
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公开(公告)号：US11985818B2
公开(公告)日：2024-05-14
申请号：US17310896
申请日：2021-03-24
发明人： ChihCheng Liu
CPC分类号： H10B20/20 , G11C29/702 , G11C29/812 , G11C2229/763
摘要： An anti-fuse device includes: a substrate; an anti-fuse gate, partially embedded in the substrate, a portion of the anti-fuse gate embedded in the substrate having one or more sharp corners; and an anti-fuse gate oxide layer, located between the anti-fuse gate and the substrate.
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