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    NANOPATTERNED SUBSTRATES
    2.
    发明申请
    NANOPATTERNED SUBSTRATES 有权

    公开(公告)号：US20240427235A1

    公开(公告)日：2024-12-26

    申请号：US18746402

    申请日：2024-06-18

    Applicant: CORNING INCORPORATED

    Inventor： Robert Alan Bellman ,  Leonard Charles Dabich, II ,  Barry James Paddock ,  Mark Alejandro Quesada ,  Bin Zhu

    IPC: G03F7/00 ,  G03F7/20 ,  G03F7/40

    Abstract: A method of forming a nanopatterned substrate includes imprinting a deposited photoresist on a substrate with a stamp to form a nanopattern including nanofeatures on the substrate, the nanofeatures including a gap therebetween. The method includes performing glancing angle deposition of a metal on the nanopattern to deposit the metal on the nanofeatures. The method includes directionally etching the nanopattern including the metal in a direction normal to a surface of the nanopattern to remove the photoresist in the gap between the nanofeatures and to expose the substrate in the gap between the nanofeatures. The method includes depositing a deposition material on the directionally etched nanopattern such that the deposition material is deposited on the exposed substrate in the gap between the nanofeatures and on the metal that is on the nanofeatures. The method also includes dissolving the deposited photoresist including the deposited deposition material thereon to remove the photoresist, the metal, and portions of the deposited deposition material that are on the photoresist from the substrate, to form the nanopatterned substrate including the deposition material deposited on the substrate in the gap between the nanofeatures.

    Methods for forming thin film transistors on a glass substrate and liquid crystal displays formed therefrom
    3.
    发明授权
    Methods for forming thin film transistors on a glass substrate and liquid crystal displays formed therefrom 有权

    公开(公告)号：US12013619B2

    公开(公告)日：2024-06-18

    申请号：US17040073

    申请日：2019-03-26

    Applicant: CORNING INCORPORATED

    Inventor： Ming-Huang Huang ,  Robert Bumju Lee ,  Rajesh Vaddi ,  Bin Zhu

    IPC: G02F1/1368 ,  H01L29/786

    CPC classification number: G02F1/1368 ,  H01L29/78681 ,  G02F1/13685

    Abstract: A thin film transistor (TFT) liquid crystal display (LCD) comprises a plurality of image pixels demarcated between an overlying liquid crystal display layer and an underlying glass substrate. Each image pixel comprises a dedicated top-gate TFT disposed over the glass substrate. Each top-gate thin film transistor comprises a process sensitive semiconductor layer disposed over the glass substrate, and a source electrode and a drain electrode disposed over the process sensitive semiconductor layer. The process sensitive semiconductor layer forms a process sensitive semiconductor active layer between the source electrode and the drain electrode and an active layer protection film is disposed over the process sensitive semiconductor active layer. A gate dielectric layer is disposed over the active layer protection film between the source electrode and the drain electrode and a gate electrode is disposed over the gate dielectric layer.

    METHODS FOR FORMING THIN FILM TRANSISTORS ON A GLASS SUBSTRATE AND LIQUID CRYSTAL DISPLAYS FORMED THEREFROM
    6.
    发明申请
    METHODS FOR FORMING THIN FILM TRANSISTORS ON A GLASS SUBSTRATE AND LIQUID CRYSTAL DISPLAYS FORMED THEREFROM 有权

    公开(公告)号：US20210018780A1

    公开(公告)日：2021-01-21

    申请号：US17040073

    申请日：2019-03-26

    Applicant: CORNING INCORPORATED

    Inventor： Ming-Huang Huang ,  Robert Bumju Lee ,  Rajesh Vaddi ,  Bin Zhu

    IPC: G02F1/1368 ,  H01L29/786

    Abstract: A thin film transistor (TFT) liquid crystal display (LCD) comprises a plurality of image pixels demarcated between an overlying liquid crystal display layer and an underlying glass substrate. Each image pixel comprises a dedicated top-gate TFT disposed over the glass substrate. Each top-gate thin film transistor comprises a process sensitive semiconductor layer disposed over the glass substrate, and a source electrode and a drain electrode disposed over the process sensitive semiconductor layer. The process sensitive semiconductor layer forms a process sensitive semiconductor active layer between the source electrode and the drain electrode and an active layer protection film is disposed over the process sensitive semiconductor active layer. A gate dielectric layer is disposed over the active layer protection film between the source electrode and the drain electrode and a gate electrode is disposed over the gate dielectric layer.

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