公开(公告)号：US20190237569A1

公开(公告)日：2019-08-01

申请号：US16376596

申请日：2019-04-05

Applicant: Cree, Inc.

Inventor： Saptharishi Sriram ,  Thomas Smith ,  Alexander Suvorov ,  Christer Hallin

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L21/746 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

公开(公告)号：US10192980B2

公开(公告)日：2019-01-29

申请号：US15424209

申请日：2017-02-03

Applicant: Cree, Inc.

Inventor： Saptharishi Sriram ,  Alexander Suvorov ,  Christer Hallin

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20 ,  H01L29/167 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10 ,  H01L29/40

Abstract: The disclosure is directed to a high-electron mobility transistor that includes a SiC substrate layer, a GaN buffer layer arranged on the SiC substrate layer, and a p-type material layer having a length parallel to a surface of the SiC substrate layer over which the GaN buffer layer is provided. The p-type material layer is provided in one of the following: the SiC substrate layer and a first layer arranged on the SiC substrate layer. A method of making the high-electron mobility transistor is also disclosed.

公开(公告)号：US11862719B2

公开(公告)日：2024-01-02

申请号：US17123727

申请日：2020-12-16

Applicant: CREE, INC.

Inventor： Saptharishi Sriram ,  Thomas Smith ,  Alexander Suvorov ,  Christer Hallin

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/1066 ,  H01L29/41766

Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

公开(公告)号：US20200258742A1

公开(公告)日：2020-08-13

申请号：US16269837

申请日：2019-02-07

Applicant: Cree, Inc.

Inventor： Alexander Suvorov ,  Robert Leonard ,  Edward Robert Van Brunt

IPC: H01L21/04 ,  H01L21/265 ,  H01L29/06

Abstract: The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant.

公开(公告)号：US20170373178A1

公开(公告)日：2017-12-28

申请号：US15424209

申请日：2017-02-03

Applicant: Cree, Inc.

Inventor： Saptharishi Sriram ,  Alexander Suvorov ,  Christer Hallin

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/167 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7787 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/7783

Abstract: The disclosure is directed to a high-electron mobility transistor that includes a SiC substrate layer, a GaN buffer layer arranged on the SiC substrate layer, and a p-type material layer having a length parallel to a surface of the SiC substrate layer over which the GaN buffer layer is provided. The p-type material layer is provided in one of the following: the SiC substrate layer and a first layer arranged on the SiC substrate layer. A method of making the high-electron mobility transistor is also disclosed.

公开(公告)号：US10892356B2

公开(公告)日：2021-01-12

申请号：US16376596

申请日：2019-04-05

Applicant: Cree, Inc.

Inventor： Saptharishi Sriram ,  Thomas Smith ,  Alexander Suvorov ,  Christer Hallin

IPC: H01L27/088 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10

Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

公开(公告)号：US09929284B1

公开(公告)日：2018-03-27

申请号：US15349092

申请日：2016-11-11

Applicant: Cree, Inc.

Inventor： Qingchun Zhang ,  Alexander Suvorov

IPC: H01L29/49 ,  H01L29/872 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/15 ,  H01L21/04

CPC classification number: H01L29/872 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606

Abstract: A Schottky diode includes a drift region doped with dopants having a first conductivity type, first and second blocking junctions that are doped with dopants having a second conductivity type in an upper portion of the drift region, first and second local current spreading layers doped with dopants having the first conductivity type underneath the respective first and second blocking junctions, and first and second contacts on respective lower and upper portions of the drift region. A channel is provided in the upper portion of the drift region between the first and second blocking junctions, the channel doped with dopants having the first conductivity type and a concentration of dopants in at least a first portion of the channel being lower than the concentration of dopants in the first and second local current spreading layers.

公开(公告)号：US20210066081A1

公开(公告)日：2021-03-04

申请号：US16950414

申请日：2020-11-17

Applicant: Cree, Inc.

Inventor： Alexander Suvorov ,  Robert Leonard ,  Edward Robert Van Brunt

IPC: H01L21/04 ,  H01L29/06 ,  H01L21/265

Abstract: The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant.