公开(公告)号：US5638006A

公开(公告)日：1997-06-10

申请号：US453322

申请日：1995-05-30

申请人： Subhash R. Nariani ,  Calvin T. Gabriel

发明人： Subhash R. Nariani ,  Calvin T. Gabriel

IPC分类号： G01R31/28 ,  H01L21/66 ,  G01R31/26

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  H01L22/12 ,  H01L22/14

摘要： An IC wafer containing thin oxide is fabricated to include at least two differentially-sized plate areas that may be upper plates of capacitors, or gates of associated MOS transistors. Before testing, the thin gate oxide underlying these plate areas is intentionally stressed by applying a stress current between these plates and the substrate. The stress current magnitude is scaled to the plate area such that each plate sees a substantially constant current density. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger plate or gate will overlie more weak oxide defects than will a plate or gate. If wafer test leakage current between the larger plate or gate and substrate exceeds leakage current between the smaller plate or gate and substrate, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the areas of the plates or gates, due to the scaling of the stress-inducing currents. Thus, if test leakage current on the wafer is substantially the same for the large and small sized plates or gates, charge-damaged oxide is indicated because the damage is not area dependent. If desired, defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices. The gate-like plates (and if present associated MOS devices) are sufficiently small to be fabricated within scribe lines of the wafer to be tested.

摘要翻译： 包含薄氧化物的IC晶片被制造成包括至少两个不同尺寸的板区域，其可以是电容器的上板，或者相关联的MOS晶体管的栅极。 在测试之前，通过在这些板和衬底之间施加应力电流来有意地强调这些板区域下面的薄栅极氧化物。 应力电流大小被缩放到板区域，使得每个板看到基本上恒定的电流密度。 由于弱的氧化物缺陷在整个薄氧化物中有一些均匀的发生，所以与板或栅极相比，较大的板或栅极将覆盖更多的弱氧化物缺陷。 如果较大的板或栅极和衬底之间的晶片测试漏电流超过较小的板或栅极和衬底之间的漏电流，则表示弱氧化物，因为缺陷是面积依赖的。 相反，由于应力诱导电流的缩放，电荷诱导的损伤基本上与板或栅极的区域无关。 因此，如果大型和小型板或栅极上的晶片上的测试漏电流基本相同，则表示电荷损坏的氧化物，因为损坏不是区域依赖的。 如果需要，可以通过检查测试MOS器件的特性来识别薄（栅极）氧化物中的缺陷。 栅极板（以及如果存在相关联的MOS器件）足够小以在要测试的晶片的划线内制造。

公开(公告)号：US5328865A

公开(公告)日：1994-07-12

申请号：US11084

申请日：1993-01-29

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

摘要： A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.

摘要翻译： 一种制造抗熔丝结构的方法，其特征在于形成导电基层的步骤; 在基层上形成抗熔丝层; 图案化抗熔丝层以形成抗熔丝岛; 在反熔丝岛上形成绝缘层; 形成通过所述绝缘层到所述反熔丝岛的通孔; 在所述绝缘层上并在所述通孔内形成导电连接层; 以及图案化所述导电连接层以形成与所述反熔丝岛的导电接触。 优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。

公开(公告)号：US5548224A

公开(公告)日：1996-08-20

申请号：US376590

申请日：1995-01-20

申请人： Calvin T. Gabriel ,  Subhash R. Nariani

发明人： Calvin T. Gabriel ,  Subhash R. Nariani

IPC分类号： G01R31/28 ,  H01L21/66 ,  G01R31/26

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  H01L22/12 ,  H01L22/14

摘要： An IC wafer containing thin oxide is fabricated with at least one pair of antenna structures having identical antenna ratio A.sub.R but different antenna plate areas. Each antenna structure includes connected-together conductive plate regions, one plate formed over thick field oxide and the other plate formed over thin oxide on the IC. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger antenna structure will overlie more weak oxide defects than will a smaller antenna structure. If wafer test leakage current across the larger antenna structure exceeds leakage current across the smaller antenna structure, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the area of the antenna plates. Because the A.sub.R ratios are constant, charge density is constant in the antenna structure portions overlying the thin oxide. If test leakage current on the wafer is substantially the same for each antenna structure, charge-damaged oxide is indicated because the damage is not area dependent. If desired, test MOS devices may be fabricated whose gates are the plates formed over the thin oxide. Defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices.

摘要翻译： 制造含有薄氧化物的IC晶片，其具有至少一对天线结构，天线结构具有相同的天线比AR但不同的天线板面积。 每个天线结构包括连接在一起的导电板区域，一个板形成在厚场氧化物上，另一个板形成在IC上的薄氧化物上。 由于弱的氧化物缺陷在整个薄氧化物中有些均匀地发生，所以与较小的天线结构相比，较大的天线结构将覆盖更多的弱氧化物缺陷。 如果跨越较大天线结构的晶片测试漏电流超过较小天线结构的漏电流，则表示弱氧化物，因为缺陷是面积依赖的。 相反，电荷引起的损伤基本上与天线板的面积无关。 由于AR比率恒定，覆盖薄氧化物的天线结构部分的电荷密度是恒定的。 如果晶片上的测试泄漏电流对于每个天线结构基本相同，则表示电荷损坏的氧化物，因为损伤不是区域依赖性的。 如果需要，可以制造测试MOS器件，其栅极是在薄氧化物上形成的板。 可以通过检查测试MOS器件的特性来识别薄（栅极）氧化物中的缺陷。

公开(公告)号：US5120679A

公开(公告)日：1992-06-09

申请号：US710220

申请日：1991-06-04

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的基底上的氧化物层，设置在开口内并接触基底的非晶硅材料以及衬在非晶硅内形成的凹陷壁的氧化物间隔物 。 间隔物通过覆盖形成在非晶硅材料中的尖头来防止抗熔丝结构的故障。 本发明的方法形成上述反熔丝结构，并且进一步解决了从抗熔丝结构位置之外的区域去除不想要的隔离材料的问题。

公开(公告)号：US5290734A

公开(公告)日：1994-03-01

申请号：US736162

申请日：1991-07-26

申请人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

发明人： William J. Boardman ,  David P. Chan ,  Kuang-Yeh Chang ,  Calvin T. Gabriel ,  Vivek Jain ,  Subhash R. Nariani

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/283 ,  H01L21/311

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

摘要： An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.

摘要翻译： 一种抗熔丝结构，其特征在于基底，形成在其上形成有开口的衬底上的氧化物层，设置在开口内并接触衬底的非晶硅材料，设置在非晶态上的导电保护材料，例如钛钨 硅材料和衬在保护材料内形成的凹部的壁上的氧化物间隔物。 保护材料和间隔物为反熔丝结构提供更严格的编程电压分布，并有助于防止反熔丝故障。

公开(公告)号：US06391766B1

公开(公告)日：2002-05-21

申请号：US09788641

申请日：2001-02-21

申请人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

发明人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

摘要： A method of forming an interconnect structure in which an organic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An inorganic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

摘要翻译： 一种形成互连结构的方法，其中有机低k介电材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 无机低k介电材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。

公开(公告)号：US6057245A

公开(公告)日：2000-05-02

申请号：US233640

申请日：1999-01-19

申请人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： H01L21/3205 ,  B24B7/22 ,  B24D13/14 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/302

CPC分类号： B24B7/228 ,  B24D13/14 ,  H01L21/31053

摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

公开(公告)号：US5990561A

公开(公告)日：1999-11-23

申请号：US97318

申请日：1998-06-12

申请人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L2924/0002

摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

摘要翻译： 根据本发明的使用钨丝塞的集成电路胶层的制造方法包括：（A）提供具有表面，中心，边缘和与该表面垂直的方向的基板; 和（B）在衬底的表面上溅射沉积胶层，使得在垂直于衬底边缘表面的方向上测量的胶层的边缘厚度为胶的中心厚度的至少105％ 层在垂直于衬底中心表面的方向上测量。 在一些实施例中，在垂直于衬底边缘处的表面的方向上测量的所述胶层的边缘厚度在胶层的中心厚度的约105％至150％的范围内，其测量方向是垂直于 在基板的中心处的表面，例如在垂直于基板中心的表面的方向上测量的胶层的中心厚度的约110％至120％的范围内。

公开(公告)号：US5804502A

公开(公告)日：1998-09-08

申请号：US786366

申请日：1997-01-16

申请人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L2924/0002

摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

公开(公告)号：US5702978A

公开(公告)日：1997-12-30

申请号：US640092

申请日：1996-04-30

申请人： Calvin T. Gabriel ,  Olivier F. Laparra

发明人： Calvin T. Gabriel ,  Olivier F. Laparra

IPC分类号： H01L21/32 ,  H01L21/76

CPC分类号： H01L21/32

摘要： A method of fabricating an integrated circuit on a silicon substrate in such a manner as to avoid the requirement of over-etching the polysilicon usually necessary to prevent shorting of adjacent devices by poly filaments caused by deep polysilicon pockets in notch areas created in the field oxide during its growth. The notches are prevented by forming the nitride mask with sloped rather than perpendicular side walls. The sloped side walls present less resistance to the growing oxide than does the usual perpendicular wall and thus does not dig into the growing oxide to form the notches. The edge of the resultant field oxide is therefore smoother, permitting easier and more complete removal of the polysilicon without the need for over-etching.

摘要翻译： 一种在硅衬底上制造集成电路的方法，以避免过度蚀刻通常必需的多晶硅的需要，以防止由在场氧化物中产生的缺口区域中的深多晶硅袋引起的由多晶丝短路的多晶丝 在它的成长期间。 通过用倾斜而不是垂直的侧壁形成氮化物掩模来防止缺口。 倾斜的侧壁比通常的垂直壁对生长的氧化物具有较小的抵抗力，因此不会进入生长的氧化物以形成凹口。 因此，所得到的场氧化物的边缘更平滑，允许更容易且更完全地去除多晶硅，而不需要过度蚀刻。