公开(公告)号：US06255210B1

公开(公告)日：2001-07-03

申请号：US09344641

申请日：1999-06-25

申请人： Rao V. Annapragada ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Milind G. Weling

IPC分类号： H01L214763

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component. The sputtering component is configured to substantially remove the oxide pyramids from over the plurality of patterned conductive features. Preferably, the plurality of patterned conductive features are either patterned metallization features or patterned polysilicon features.

公开(公告)号：US06777344B2

公开(公告)日：2004-08-17

申请号：US09782678

申请日：2001-02-12

申请人： Rao V. Annapragada ,  Ian J. Morey ,  Chok W. Ho

发明人： Rao V. Annapragada ,  Ian J. Morey ,  Chok W. Ho

IPC分类号： H01L21302

CPC分类号： H01L21/31138 ,  G03F7/427

摘要： Process for stripping photoresist from a semiconductor wafer formed with at least one layer of OSG dielectric. The stripping process may be formed in situ or ex situ with respect to other integrated circuit fabrication processes. The process includes a reaction may be oxidative or reductive in nature. The oxidative reaction utilizes an oxygen plasma. The reductive reaction utilizes an ammonia plasma. The process of the present invention results in faster ash rates with less damage to the OSG dielectric than previously known stripping methods.

摘要翻译： 从形成有至少一层OSG电介质的半导体晶片剥离光致抗蚀剂的方法。 剥离过程可以相对于其它集成电路制造工艺原位或非原地形成。 该方法包括反应可以是氧化还原性的。 氧化反应利用氧等离子体。 还原反应使用氨等离子体。 本发明的方法导致更快的灰分速率，比以前已知的剥离方法对OSG电介质的损伤更小。

公开(公告)号：US06303192B1

公开(公告)日：2001-10-16

申请号：US09121180

申请日：1998-07-22

申请人： Rao V. Annapragada ,  Tekle M. Tafari ,  Subhas Bothra

发明人： Rao V. Annapragada ,  Tekle M. Tafari ,  Subhas Bothra

IPC分类号： C23C1416

CPC分类号： H01L21/02137 ,  C23C16/0272 ,  C23C16/505 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO2 skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO2 skin.

摘要翻译： 一种制造多层集成电路结构的方法，包括在衬底上沉积甲基化合物旋涂在玻璃层上。 通过等离子体沉积处理玻璃层上的旋涂，在玻璃层上的甲基化合物旋涂上形成SiO 2皮肤，然后通过等离子体沉积再次处理以形成粘附于SiO 2皮肤的盖层。

公开(公告)号：US6057245A

公开(公告)日：2000-05-02

申请号：US233640

申请日：1999-01-19

申请人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： H01L21/3205 ,  B24B7/22 ,  B24D13/14 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/302

CPC分类号： B24B7/228 ,  B24D13/14 ,  H01L21/31053

摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

公开(公告)号：US06700200B1

公开(公告)日：2004-03-02

申请号：US09715973

申请日：2000-11-16

申请人： Rao V. Annapragada

发明人： Rao V. Annapragada

IPC分类号： H01L2348

CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76826

摘要： Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical dehydroxylation operation, wherein the halogen compound may be NH4F or CCl4.

摘要翻译： 公开了一种在半导体器件层中制造可靠的通孔的方法，以及具有疏水性的内壁表面层，从而不吸湿的可靠的通孔结构。 通孔结构的内壁具有具有旋转玻璃（SOG）特性的材料层，使得其特征在于SOG的外层在光致抗蚀剂灰化期间氧化，以在通孔中形成二氧化硅的表面层 孔壁。 在该方法中，在灰化操作之后通过化学脱羟基化操作放置通孔结构，使得通孔壁中的二氧化硅层转化为疏水材料层。 通过引入适于化学脱羟基操作的卤素化合物进行转化，其中卤素化合物可以是NH 4 F或CCl 4。

公开(公告)号：US6165905A

公开(公告)日：2000-12-26

申请号：US234235

申请日：1999-01-20

申请人： Rao V. Annapragada

发明人： Rao V. Annapragada

IPC分类号： H01L21/768 ,  B05D3/02

CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76826

摘要： Disclosed is a method of making a reliable via hole in a semiconductor device layer, and a reliable via structure having internal wall surface layers that are hydrophobic, and thereby are non-moisture absorbing. The inner wall of the via structure has a layer of material having a characteristic of spin on glass (SOG), such that the characteristic is that the outer layer of the SOG oxidizes during photoresist ashing to form a surface layer of silicon dioxide in the via hole wall. In the method, the via structure is placed through a chemical dehydroxylation operation after the ashing operation, such that the layer of silicon dioxide in the via hole wall is converted into a hydrophobic material layer. The conversion is performed by introducing a halogen compound suitable for the chemical hydroxilation operation, wherein the halogen compound may be NH.sub.4 F or CCl.sub.4.

摘要翻译： 公开了一种在半导体器件层中制造可靠的通孔的方法，以及具有疏水性的内壁表面层，从而不吸湿的可靠的通孔结构。 通孔结构的内壁具有具有旋转玻璃（SOG）特性的材料层，使得其特征在于SOG的外层在光致抗蚀剂灰化期间氧化，以在通孔中形成二氧化硅的表面层 孔壁。 在该方法中，在灰化操作之后通过化学脱羟基化操作放置通孔结构，使得通孔壁中的二氧化硅层转化为疏水材料层。 通过引入适于化学氢化操作的卤素化合物进行转化，其中卤素化合物可以是NH 4 F或CCl 4。

公开(公告)号：US06380092B1

公开(公告)日：2002-04-30

申请号：US09516333

申请日：2000-03-01

申请人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： H01L21302

CPC分类号： B24B7/228 ,  B24D13/14 ,  H01L21/31053

摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

摘要翻译： 一种用于半导体晶片的气相平面化工艺。 本发明包括用于半导体晶片的干式平坦化的系统和方法。 例如，本发明包括适于通过施加干磨和干化学来有效地去除半导体晶片的电介质材料层的全部或一部分的系统。 因此，本发明的系统平坦化电介质材料的高度差异，因为比低面积更快地除去高面积的形貌。 具体地，本发明的一个实施例利用干研磨抛光垫在真空平坦化室内研磨半导体晶片的期望表面。 研磨抛光垫的结果是磨损表面，破坏了电介质表面材料薄层的化学键。 一旦化学键断裂，等离子体气体内的反应性基团就会与表面材料发生化学反应，从而形成高挥发性的气态物质。 换句话说，等离子体气体用于从电介质层去除先前机械抛光的材料。 随后，将新形成的气态物质从真空平坦化室中除去。 从半导体晶片的表面去除材料的过程继续进行，直到表面被充分平坦化。 以这种方式，本发明提供了用于使半导体晶片的表面平坦化的干法。

公开(公告)号：US06218735B1

公开(公告)日：2001-04-17

申请号：US09439021

申请日：1999-11-12

申请人： Rao V. Annapragada

发明人： Rao V. Annapragada

IPC分类号： H01L2131

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31053 ,  H01L21/3121 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76829 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH3SiH3, increasing the flow of SiH4 and keeping the flow of H2O2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO2 skin.

摘要翻译： 一种用于制造多层集成电路结构的方法，包括在衬底上沉积甲基掺杂的氧化硅层。 通过减少CH 3 SiH 3的流量，增加SiH 4的流动并保持H 2 O 2的流动持续一段时间，将SiO2表面沉积在甲基掺杂的氧化硅层上。 最后，沉积粘附到SiO 2皮肤的盖层。

公开(公告)号：US6001747A

公开(公告)日：1999-12-14

申请号：US120895

申请日：1998-07-22

申请人： Rao V. Annapragada

发明人： Rao V. Annapragada

IPC分类号： C23C16/40 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01R9/11

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76829 ,  H01L23/5329 ,  H01L21/31053 ,  H01L21/3121 ,  H01L2924/0002

摘要： A method for making a multi-layered integrated circuit structure, includes depositing a methyl doped silicon oxide layer over a substrate. SiO.sub.2 skin is deposited on the methyl doped silicon oxide layer by decreasing the flow of CH.sub.3 SiH.sub.3, increasing the flow of SiH.sub.4 and keeping the flow of H.sub.2 O.sub.2 constant for a period of time. Finally, a cap layer is deposited which adheres to the SiO.sub.2 skin.

摘要翻译： 一种用于制造多层集成电路结构的方法，包括在衬底上沉积甲基掺杂的氧化硅层。 通过减少CH 3 SiH 3的流量，增加SiH 4的流动并保持H 2 O 2的流动持续一段时间，将SiO2表面沉积在甲基掺杂的氧化硅层上。 最后，沉积粘附到SiO 2皮肤的盖层。

公开(公告)号：US07534363B2

公开(公告)日：2009-05-19

申请号：US10877222

申请日：2004-06-25

申请人： Rao V. Annapragada ,  Odette Turmel ,  Kenji Takeshita ,  Lily Zheng ,  Thomas S. Choi ,  David R. Pirkle

发明人： Rao V. Annapragada ,  Odette Turmel ,  Kenji Takeshita ,  Lily Zheng ,  Thomas S. Choi ,  David R. Pirkle

IPC分类号： C23F1/00

CPC分类号： H01J37/3244 ,  G03F7/427 ,  H01J37/32082 ,  H01L21/31116 ,  H01L21/31138

摘要： A method for removing organic material over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to an outer zone of the plasma processing chamber, wherein the outer zone surrounds the inner zone and the second gas has a carbon containing component, wherein a concentration of the carbon containing component of the second gas is greater than a concentration of the carbon containing component in the first gas. Plasmas are simultaneously generated from the first gas and second gas. Some or all of the organic material is removed using the generated plasmas.

摘要翻译： 提供了一种在衬底上除去有机材料的方法。 将基板放置在等离子体处理室中。 第一气体被提供到等离子体处理室内的内部区域。 第二气体被提供到等离子体处理室的外部区域，其中外部区域围绕内部区域，第二气体具有含碳成分，其中第二气体的含碳成分的浓度大于浓度 的第一气体中的含碳组分。 从第一气体和第二气体同时产生等离子体。 使用所产生的等离子体去除部分或全部有机材料。