公开(公告)号：US6057245A

公开(公告)日：2000-05-02

申请号：US233640

申请日：1999-01-19

申请人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： H01L21/3205 ,  B24B7/22 ,  B24D13/14 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/302

CPC分类号： B24B7/228 ,  B24D13/14 ,  H01L21/31053

摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

公开(公告)号：US06267076B1

公开(公告)日：2001-07-31

申请号：US09516341

申请日：2000-03-01

申请人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： C23F112

CPC分类号： B24B7/228 ,  B24D13/14 ,  H01L21/31053

摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.

摘要翻译： 一种用于半导体晶片的气相平面化工艺。 本发明包括用于半导体晶片的干式平坦化的系统和方法。 例如，本发明包括适于通过施加干磨和干化学来有效地去除半导体晶片的电介质材料层的全部或一部分的系统。 因此，本发明的系统平坦化电介质材料的高度差异，因为比低面积更快地除去高面积的形貌。

公开(公告)号：US06380092B1

公开(公告)日：2002-04-30

申请号：US09516333

申请日：2000-03-01

申请人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： H01L21302

CPC分类号： B24B7/228 ,  B24D13/14 ,  H01L21/31053

摘要： A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material. Once the chemical bonds are broken, reactive radicals within a plasma gas chemically react with the surface material thereby forming a gaseous species which is highly volatile. In other words, the plasma gas is used to remove previously mechanically polished material from the dielectric layer. Subsequently, the newly formed gaseous species is removed from the vacuum planarization chamber. This process of removing material from the surface of the semiconductor wafer continues until the surface is sufficiently planarized. In this manner, the present invention provides a dry process for planarizing a surface of a semiconductor wafer.

摘要翻译： 一种用于半导体晶片的气相平面化工艺。 本发明包括用于半导体晶片的干式平坦化的系统和方法。 例如，本发明包括适于通过施加干磨和干化学来有效地去除半导体晶片的电介质材料层的全部或一部分的系统。 因此，本发明的系统平坦化电介质材料的高度差异，因为比低面积更快地除去高面积的形貌。 具体地，本发明的一个实施例利用干研磨抛光垫在真空平坦化室内研磨半导体晶片的期望表面。 研磨抛光垫的结果是磨损表面，破坏了电介质表面材料薄层的化学键。 一旦化学键断裂，等离子体气体内的反应性基团就会与表面材料发生化学反应，从而形成高挥发性的气态物质。 换句话说，等离子体气体用于从电介质层去除先前机械抛光的材料。 随后，将新形成的气态物质从真空平坦化室中除去。 从半导体晶片的表面去除材料的过程继续进行，直到表面被充分平坦化。 以这种方式，本发明提供了用于使半导体晶片的表面平坦化的干法。

公开(公告)号：US06255210B1

公开(公告)日：2001-07-03

申请号：US09344641

申请日：1999-06-25

申请人： Rao V. Annapragada ,  Milind G. Weling

发明人： Rao V. Annapragada ,  Milind G. Weling

IPC分类号： H01L214763

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating inter-metal oxide in semiconductor devices and semiconductor devices is provided. The method begins by providing a semiconductor substrate having a plurality of patterned conductive features. The method then moves to where a high density plasma (HDP) operation is performed and is configured to deposit an oxide layer over the plurality of patterned conductive features. The HDP operation includes a deposition component and a sputtering component. The deposition component is driven by a deposition gas and the sputtering component is driven by a sputtering gas. The HDP operation forms oxide pyramids over the plurality of patterned conductive features. The method now moves to where the deposition gas is removed to close off the deposition component in the HDP operation. Now, the HDP operation is run with the sputtering gas while retaining the sputtering component. The sputtering component is configured to substantially remove the oxide pyramids from over the plurality of patterned conductive features. Preferably, the plurality of patterned conductive features are either patterned metallization features or patterned polysilicon features.

公开(公告)号：US5861342A

公开(公告)日：1999-01-19

申请号：US579605

申请日：1995-12-26

申请人： Calvin T. Gabriel ,  Milind G. Weling

发明人： Calvin T. Gabriel ,  Milind G. Weling

IPC分类号： H01L21/3105 ,  H01L21/461 ,  H01L21/44

CPC分类号： H01L21/31051 ,  Y10S438/926

摘要： A method of improving the planarity of spin-on-glass layers in semiconductor wafer processing is disclosed. Gaps in between active conductive traces in a trace layer that exceed a predetermined distance are provided with dummy lines having a specific geometry in order to improve the planarity achieved in subsequently applied spin-on glass layers. In some embodiments, the predetermined distance is greater than approximately 1 micrometer, as for example in the range of approximately 3 to 6 micrometers. In some applications, both the active conductive traces and the dummy lines are formed from a metallic material that is deposited in one single step with a passivation layer being deposited over both the conductive traces and the raised lines prior to application of the spin-on glass layer.

摘要翻译： 公开了一种提高半导体晶片处理中旋涂玻璃层的平面度的方法。 具有超过预定距离的迹线层中的有源导电迹线之间的间隙被提供有具有特定几何形状的虚拟线，以便改善随后施加的旋涂玻璃层中实现的平面度。 在一些实施例中，预定距离大于约1微米，例如在约3至6微米的范围内。 在一些应用中，有源导电迹线和虚拟线都由金属材料形成，金属材料在一个单一步骤中沉积，在施加旋涂玻璃之前，钝化层沉积在导电迹线和凸起线上方 层。

公开(公告)号：US5639697A

公开(公告)日：1997-06-17

申请号：US593900

申请日：1996-01-30

申请人： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

发明人： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

IPC分类号： H01L21/3105 ,  H01L21/302 ,  H01L21/463

CPC分类号： H01L21/31053 ,  Y10S438/926

摘要： A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

摘要翻译： 公开了用于不同层的半导体晶片的形貌图案密度的方法，以改进在晶片处理期间使用的化学机械抛光工艺。 为了实现晶片表面上的预定图案形状密度，根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。 在一些实施例中，预定图案密度在大约40％至80％的范围内。 在一些应用中，活性导电迹线和虚拟凸起线都由金属材料形成，该金属材料在化学机械抛光过程之前在一个步骤中沉积，绝缘层沉积在两个有源导电迹线和虚拟凸起线上 。 在其他应用中，假凸起线由绝缘层形成。

公开(公告)号：US5965941A

公开(公告)日：1999-10-12

申请号：US734501

申请日：1996-10-21

申请人： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

发明人： Milind G. Weling ,  Subhas Bothra ,  Calvin T. Gabriel

IPC分类号： H01L21/3105 ,  H01L23/48 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L21/31053 ,  Y10S438/926

摘要： A method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.

摘要翻译： 公开了用于不同层的半导体晶片的形貌图案密度的方法，以改进在晶片处理期间使用的化学机械抛光工艺。 为了实现晶片表面上的预定图案形状密度，根据需要将虚拟凸起线插入到迹线层上的有源导电迹线之间的间隙中。 在一些实施例中，预定图案密度在大约40％至80％的范围内。 在一些应用中，有源导电迹线和虚拟凸起线都是由金属材料形成的，该金属材料在化学机械抛光过程之前沉积在一个单一步骤中，绝缘层沉积在两个有源导电迹线和虚拟凸起线上 。 在其他应用中，假凸起线由绝缘层形成。

公开(公告)号：US06916525B2

公开(公告)日：2005-07-12

申请号：US10666484

申请日：2003-09-19

申请人： Subhas Bothra ,  Milind G. Weling

发明人： Subhas Bothra ,  Milind G. Weling

IPC分类号： B24B37/013 ,  B24B49/10 ,  H01L21/3105 ,  B32B9/04 ,  B32B3/00

CPC分类号： B24B37/013 ,  B24B49/10 ,  H01L21/31053 ,  Y10T428/24917

摘要： A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

摘要翻译： 使用具有优化的光学性质的膜用于化学机械抛光（CMP）端点检测的方法。 具体地，本发明的一个实施方案包括用于改进化学机械抛光终点检测的方法。 该方法包括在反射停止层上沉积介电层的步骤。 反射阻挡层设置在配置在半导体晶片上的部件的上方。 在使用光的反射信号确定介电层的厚度期间，反射率停止层基本上减少了从组件反射的任何光。 因此，本发明提供了一种在半导体晶片的CMP工艺期间提供更准确的端点检测的方法和系统。 作为本发明的结果，CMP机器的操作者精确地知道何时停止半导体晶片的CMP工艺。 此外，本发明使得CMP机器的操作者能够在半导体晶片的CMP处理之后以一定的精度了解剩余的膜（例如介电层）的厚度。 此外，本发明基本上消除了半导体晶片的过度的化学机械抛光。 因此，为了补偿半导体晶片的过度的化学机械抛光，不需要在晶片上沉积太多的介电材料。 因此，本发明能够降低半导体晶片的制造成本。

公开(公告)号：US5618757A

公开(公告)日：1997-04-08

申请号：US593898

申请日：1996-01-30

申请人： Subhas Bothra ,  Milind G. Weling

发明人： Subhas Bothra ,  Milind G. Weling

IPC分类号： H01L21/3105 ,  H01L21/302 ,  H01L21/304 ,  H01L21/463

CPC分类号： H01L21/31053 ,  Y10S438/926 ,  Y10S438/941

摘要： Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised areas are formed from a metallic material that is deposited in one single step with an oxide layer deposited over both the active conductive traces and the dummy raised areas prior to the application of spin-on glass and the spin-on glass etchback process. In other applications, the dummy raised areas are formed from an oxide material.

摘要翻译： 旋转玻璃回蚀是通常用于在制造期间平面化半导体晶片的表面的技术。 旋涂玻璃的蚀刻速率很大程度上受到旋涂玻璃回蚀工艺中暴露的氧化物的影响。 在旋涂玻璃回蚀期间暴露的氧化物的量取决于地形的底层图案密度。 公开了一种标准化不同层半导体晶片的形貌图案密度的方法，以改善用于在处理期间平坦化晶片表面的旋涂玻璃回蚀工艺。 为了实现晶片表面的标准图案密度，虚拟凸起区域被添加到迹线层上的有源导电迹线之间的间隙中。 在一些实施方案中，标准化图案密度在约40％至80％的范围内。 在一些应用中，有源导电迹线和虚拟凸起区域均由金属材料形成，该金属材料在施加旋转之前沉积在两个有源导电迹线和虚拟凸起区域上的一个单一步骤中沉积， 在玻璃上和旋涂玻璃回蚀工艺。 在其他应用中，虚拟凸起区域由氧化物材料形成。

公开(公告)号：US5653622A

公开(公告)日：1997-08-05

申请号：US506664

申请日：1995-07-25

申请人： Charles Drill ,  Milind G. Weling

发明人： Charles Drill ,  Milind G. Weling

IPC分类号： B24B37/10 ,  B24B49/16 ,  B24B53/007 ,  B24B53/017 ,  B24B49/00 ,  B24B7/22

CPC分类号： B24B37/107 ,  B24B49/16 ,  B24B53/017

摘要： A chemical mechanical polishing system for processing semiconductor wafers has a polishing arm and carrier assembly that press the topside surface of a semiconductor wafer against a motor driven, rotating polishing pad. Improved uniformity of material removal, as well as improved stability of material removal rate, is achieved through the use of a controller that applies a variable wafer backside pressure to the wafers being polished. More specifically, a control subsystem maintains a wafer count, corresponding to how many wafers have been polished by the polishing pad. The control subsystem regulates the backside pressure applied to each wafer in accordance with a predetermined function such that the backside pressure increases monotonically as the wafer count increases. In the preferred embodiment, the control system regulates the backside pressure in accordance with a linear function of the form: Backside Pressure=A+(B.times.Wafer Count). Whenever a new polishing pad is mounted, the wafer count value is reset to a predefined minimum wafer count value and the backside pressure for the next wafer to be polished is reset to a preset minimum backside pressure value.

摘要翻译： 用于处理半导体晶片的化学机械抛光系统具有抛光臂和载体组件，其将半导体晶片的顶侧表面抵靠电动机驱动的旋转抛光垫。 通过使用向待抛光的晶片施加可变晶片背面压力的控制器来实现材料去除的均匀性提高以及改善材料去除速率的稳定性。 更具体地说，控制子系统保持晶片计数，对应于由抛光垫抛光了多少个晶片。 控制子系统根据预定功能调节施加到每个晶片的背侧压力，使得当晶片计数增加时背侧压力单调增加。 在优选实施例中，控制系统根据以下形式的线性函数来调节背侧压力：背压= A +（BxWafer计数）。 每当安装新的抛光垫时，将晶片计数值重新设置为预定的最小晶片计数值，并将待抛光的下一个晶片的背侧压力重置为预设的最小背侧压力值。