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公开(公告)号：US06865725B2
公开(公告)日：2005-03-08
申请号：US10249639
申请日：2003-04-28
CPC分类号： G06F17/5045 , G06F17/5077
摘要： A method for designing integrated circuits comprising: partitioning interconnects of an integrated circuit design based on partition criteria to create sets of interconnect partitions; selecting at least one analysis method from a set of analysis methods to be performed on interconnects of each set of interconnect partitions; and performing each selected analysis method on interconnects of each corresponding interconnect partition.
摘要翻译： 一种用于设计集成电路的方法，包括：基于分区准则划分集成电路设计的互连以创建一组互连分区; 从在每组互连分区的互连上执行的一组分析方法中选择至少一种分析方法; 以及在每个对应的互连分区的互连上执行每个选择的分析方法。
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公开(公告)号：US06950997B2
公开(公告)日：2005-09-27
申请号：US10249640
申请日：2003-04-28
CPC分类号： G06F17/5045
摘要： A method for designing an integrated circuit by a user, including: evaluating noise parameters for design elements of an integrated circuit design; determining if the noise parameters meet noise constraints of the integrated circuit design; and if the noise parameters do not meet the noise constraints, selecting alternative design elements having noise parameters that do meet the noise constraints.
摘要翻译： 一种用户设计集成电路的方法，包括：评估集成电路设计的设计元素的噪声参数; 确定噪声参数是否满足集成电路设计的噪声限制; 并且如果噪声参数不满足噪声约束，则选择具有确实满足噪声约束的噪声参数的替代设计元件。
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公开(公告)号：US06825490B1
公开(公告)日：2004-11-30
申请号：US10605567
申请日：2003-10-09
IPC分类号： H01L2358
CPC分类号： G01R35/005
摘要： A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.
摘要翻译： 确定半导体器件内校准电阻器的实际电阻值的结构和相关方法。 半导体器件包括电容器，校准电阻器和校准电路。 施加到校准电阻器的电压产生通过校准电阻器的电流，以对电容器充电。 校准电路适于测量对电容器充电所需的实际时间。 校准电路还适用于根据电容器充电所需的实际时间和电容器的电容值来计算校准电阻器的实际电阻值。
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4.发明授权Bias-controlled deep trench substrate noise isolation integrated circuit device structures 有权偏置控制深沟槽衬底噪声隔离集成电路器件结构公开(公告)号：US08212332B2
公开(公告)日：2012-07-03
申请号：US13207480
申请日：2011-08-11
申请人： Phillip Francis Chapman , David Goren , Rajendran Krishnasamy , Benny Sheinman , Shlomo Shlafman , Raminderpal Singh , Wayne H. Woods
发明人： Phillip Francis Chapman , David Goren , Rajendran Krishnasamy , Benny Sheinman , Shlomo Shlafman , Raminderpal Singh , Wayne H. Woods
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L29/00
CPC分类号： H01L29/945 , H01L29/66181
摘要： A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.
摘要翻译： 一种用于在半导体芯片上的集成电路器件之间提供噪声隔离的新型有用的装置和方法。 本发明解决了由集成电路芯片中的数字开关器件产生的噪声的问题，该芯片可以通过硅衬底耦合到敏感的模拟电路（例如，PLL，收发器，ADC等）中，导致敏感模拟器的性能显着降低 电路。 本发明利用连接到地的深沟槽电容器（DTCAP）器件将受害电路与同一集成电路芯片上的侵扰器噪声源隔离开来。 与其他现有技术的屏蔽技术相比，电容器的深度穿透产生了深深的衬底中的接地屏蔽。
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5.发明申请公开(公告)号：US20110291238A1
公开(公告)日：2011-12-01
申请号：US13207480
申请日：2011-08-11
申请人： Phillip Francis Chapman , David Goren , Rajendran Krishnasamy , Benny Sheinman , Shlomo Shlafman , Raminderpal Singh , Wayne H. Woods
发明人： Phillip Francis Chapman , David Goren , Rajendran Krishnasamy , Benny Sheinman , Shlomo Shlafman , Raminderpal Singh , Wayne H. Woods
CPC分类号： H01L29/945 , H01L29/66181
摘要： A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques
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6.发明授权Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction 失效使用基于子电路的提取来检查布局与多指MOS晶体管布局的示意图的方法公开(公告)号：US07139990B2
公开(公告)日：2006-11-21
申请号：US10807478
申请日：2004-03-23
申请人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
发明人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
摘要翻译： 描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。 通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。 通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。 这种完整和准确的几何参数比较增强了布局物理验证的置信度。
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7.发明授权公开(公告)号：US07000214B2
公开(公告)日：2006-02-14
申请号：US10707068
申请日：2003-11-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.
摘要翻译： 一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。
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8.发明授权公开(公告)号：US08285414B2
公开(公告)日：2012-10-09
申请号：US12415348
申请日：2009-03-31
申请人： Ehud Aharoni , Robert J. Baseman , Ramona Kei , Oded Margalit , Kevin Mackey , Michal Rosen-Zvi , Raminderpal Singh , Noam Slonim , Hong Lin , Fateh A. Tipu , Adam D. Ticknor , Timothy M. McCormack
发明人： Ehud Aharoni , Robert J. Baseman , Ramona Kei , Oded Margalit , Kevin Mackey , Michal Rosen-Zvi , Raminderpal Singh , Noam Slonim , Hong Lin , Fateh A. Tipu , Adam D. Ticknor , Timothy M. McCormack
IPC分类号： G06F19/00
CPC分类号： G05B23/0216 , G05B23/0229 , G05B2219/32191 , G05B2219/32194 , G05B2219/45031 , G05B2219/50065 , Y02P90/22 , Y02P90/86 , Y10T409/309408
摘要： A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.
摘要翻译： 公开了一种用于在制造微电子器件的同时评估半导体制造工具的性能的方法和系统。 至少根据执行至少一项统计测试生成一份报告。 该报告包括至少一个具有与传感器对应的行的热图，对应于配方步骤期间获得的跟踪数据的列，以及行和列的交叉点处的单元格。 工具中至少有一个传感器获得配方步骤的痕迹数据，同时制造至少一个微电子器件。 计算设备分析所获得的跟踪数据以确定在数据中发现的操作意义的水平，并向指示操作意义水平的跟踪数据分配分数。 然后，计算设备将分数放置在热图的相应单元中。 用户使用单元格来评估刀具性能。
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9.发明授权Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuits 失效在电路原理图定制设计中最佳使用直接拟合和内插模型的方法公开(公告)号：US07089512B2
公开(公告)日：2006-08-08
申请号：US10708608
申请日：2004-03-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits. The method further comprises schematically simulating a custom circuit; back annotating to a schematic circuit which of the transistors use direct-fit models and which of the transistor devices are interpolated; determining whether the transistor devices are in any of cutoff, saturation, static linear, and dynamic linear mode during simulation of the custom circuit; removing the saturation and dynamic linear mode transistor devices; back annotating the netlist to a schematic with a predetermined device state; and performing sensitivity analysis on saturation and dynamic linear mode transistor devices.
摘要翻译： 一种分析和设计电路的方法，包括为晶体管器件创建一组内插模型; 为晶体管器件创建一组特征（直接拟合）模型; 分析网表中的晶体管器件，用于在该特征模型集合中进行匹配; 并提供在设计电路中使用匹配的特征模型或内插模型之一的选择。 该方法还包括示意性地模拟定制电路; 反向注释到晶体管中的哪一个使用直接拟合模型和晶体管器件中的哪些被内插的原理图电路; 在定制电路的仿真期间确定晶体管器件是否处于截止，饱和，静态线性和动态线性模式中的任何一种; 去除饱和和动态线性模式晶体管器件; 将网表注释到具有预定设备状态的原理图; 并对饱和和动态线性模式晶体管器件执行灵敏度分析。
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10.发明授权公开(公告)号：US06954920B2
公开(公告)日：2005-10-11
申请号：US10604174
申请日：2003-06-30
CPC分类号： G06F17/5077
摘要： A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.
摘要翻译： 一种用于专用集成电路中自动传输线选择的方法，程序产品和设计工具。 该方法包括：确定应用专用集成电路的块之间的路由路径; 扫描用于传输线替换候选的路由路径; 并且对于每个传输线替换候选，自动选择缓冲线或传输线以实现路由路径。
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