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公开(公告)号：US08299455B2
公开(公告)日：2012-10-30
申请号：US11872291
申请日：2007-10-15
IPC分类号： H01L29/06
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。
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公开(公告)号：US20120132966A1
公开(公告)日：2012-05-31
申请号：US11872291
申请日：2007-10-15
IPC分类号： H01L29/78 , H01L21/768 , H01L23/52
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。
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公开(公告)号：US08421077B2
公开(公告)日：2013-04-16
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
IPC分类号： H01L29/10
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译： 替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。 在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。 替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。 各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。 通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。
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公开(公告)号：US20120208332A1
公开(公告)日：2012-08-16
申请号：US13454709
申请日：2012-04-24
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
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公开(公告)号：US08685809B2
公开(公告)日：2014-04-01
申请号：US13454709
申请日：2012-04-24
IPC分类号： H01L21/336
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译： 自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。 具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。 在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。 接触电阻的降低又改善了通过结构的电流的流动。 除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。
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公开(公告)号：US20110298017A1
公开(公告)日：2011-12-08
申请号：US12795973
申请日：2010-06-08
申请人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
发明人： Sameer H. Jain , Carl J. Radens , Shahab Siddiqui , Jay W. Strane
CPC分类号： H01L29/7833 , H01L21/76834 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A replacement gate field effect transistor includes at least one self-aligned contact that overlies a portion of a dielectric gate cap. A replacement gate stack is formed in a cavity formed by removal of a disposable gate stack. The replacement gate stack is subsequently recessed, and a dielectric gate cap having sidewalls that are vertically coincident with outer sidewalls of the gate spacer is formed by filling the recess over the replacement gate stack. An anisotropic etch removes the dielectric material of the planarization layer selective to the material of the dielectric gate cap, thereby forming at least one via cavity having sidewalls that coincide with a portion of the sidewalls of the gate spacer. A portion of each diffusion contact formed by filling the at least one via cavity overlies a portion of the gate spacer and protrudes into the dielectric gate cap.
摘要翻译： 替代栅极场效应晶体管包括至少一个自对准接触，其覆盖在电介质栅极盖的一部分上。 在通过去除一次性栅极堆叠而形成的空腔中形成替换栅极堆叠。 替换栅极堆叠随后被凹入，并且具有与栅极间隔物的外侧壁垂直重合的侧壁的电介质栅极盖通过在该替代栅极叠层上填充该凹槽来形成。 各向异性蚀刻去除对介电栅极盖的材料有选择性的平坦化层的电介质材料，从而形成具有与栅极间隔物的侧壁的一部分重合的侧壁的至少一个通孔。 通过填充至少一个通孔形成的每个扩散接触部分覆盖在栅极间隔物的一部分上并且突出到电介质栅极帽中。
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公开(公告)号：US06989317B1
公开(公告)日：2006-01-24
申请号：US10904088
申请日：2004-10-22
申请人： Carl J. Radens , Jay W. Strane
发明人： Carl J. Radens , Jay W. Strane
IPC分类号： H01L21/76
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76808
摘要： A novel trench etching method for etching trenches of different depths which are self-aligned to one another is presented. The method comprises the steps of (a) creating first and second trenches of a same depth in a dielectric layer, wherein the second trench is wider than the first trench, (b) forming a conformal gapfill layer on top of the dielectric layer such that the conformal gapfill layer is thicker in the first trench than in the second trench, (c) etching back the conformal gapfill layer until a bottom wall of the second trench is exposed to the atmosphere while a bottom wall of the first trench is still covered by the conformal gapfill layer, (d) etching further into the dielectric layer via the second trench. As a result, the second trench is deeper than the first trench.
摘要翻译： 提出了一种用于蚀刻彼此自对准的不同深度的沟槽的新型沟槽蚀刻方法。 该方法包括以下步骤：（a）在电介质层中产生相同深度的第一和第二沟槽，其中第二沟槽比第一沟槽宽，（b）在电介质层的顶部上形成共形间隙填充层，使得 第一沟槽中的保形间隙填充层比第二沟槽厚，（c）蚀刻保形间隙填充层，直到第二沟槽的底壁暴露于大气，同时第一沟槽的底壁仍然被第一沟槽的底壁覆盖 保形间隙填充层，（d）经由第二沟槽进一步蚀刻到介电层中。 结果，第二沟槽比第一沟槽更深。
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8.发明授权Etching openings of different depths using a single mask layer method and structure 失效使用单一掩模层方法和结构蚀刻不同深度的开口公开(公告)号：US06887785B1
公开(公告)日：2005-05-03
申请号：US10709564
申请日：2004-05-13
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76816 , H01L21/76831 , H01L21/76897
摘要： A semiconductor device with openings of differing depths in a substrate or layer is described, as are related methods for its manufacture. Through selective deposition of a single mask layer, whereby low aspect ratio openings are substantially coated while high aspect ratio are at most partially coated, subsequent etching of the substrate or layer is restricted to uncoated portions of the high aspect ratio openings. The result is a substrate or layer with openings of more than one depth using a single mask layer. In a second embodiment, the selective deposition of a single mask layer is utilized to etch a layer while protecting underlying structures from etching. In a third embodiment, the selective deposition of a single mask layer is utilized to etch an opening into a layer wherein the opening has a sub-lithographic diameter, i.e., the diameter of the opening is smaller than can be achieved with the particular lithographic technique employed.
摘要翻译： 描述了在衬底或层中具有不同深度的开口的半导体器件，以及用于其制造的相关方法。 通过选择性沉积单个掩模层，由此在高纵横比最多部分涂覆的同时基本上涂覆低纵横比的开口，随后对衬底或层的蚀刻被限制在高纵横比开口的未涂覆部分。 结果是使用单个掩模层的具有多于一个深度的开口的基底或层。 在第二实施例中，使用单个掩模层的选择性沉积来蚀刻层，同时保护下面的结构免受蚀刻。 在第三实施例中，使用单个掩模层的选择性沉积来将开口蚀刻到其中开口具有亚光刻直径的开口，即，开口的直径小于可以用特定光刻技术实现的开口的直径 雇用。
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公开(公告)号：US08802990B2
公开(公告)日：2014-08-12
申请号：US13432037
申请日：2012-03-28
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： H01B5/14 , H01L21/76 , H01L21/764
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译： 连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。 使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。 形成间隙填充层以堵塞第一沟槽部分中的空间。 将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。 在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。
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公开(公告)号：US08692649B2
公开(公告)日：2014-04-08
申请号：US13296242
申请日：2011-11-15
IPC分类号： H04Q9/00
CPC分类号： G08B13/14 , G06Q10/087
摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.
摘要翻译： 用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。 键码单元位于受保护的环境中，与资产管理区域有关。 设备单元可以存储设备标识码。 键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备 如果设备移动到资产管理区域外，则单元从密钥单元接收。
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