公开(公告)号：US20060028895A1

公开(公告)日：2006-02-09

申请号：US10914255

申请日：2004-08-09

申请人： Carl Taussig ,  Warren Jackson ,  Craig Perlov ,  Frank Jeffrey

发明人： Carl Taussig ,  Warren Jackson ,  Craig Perlov ,  Frank Jeffrey

IPC分类号： G11C17/18 ,  G11C11/36

CPC分类号： H01L23/5252 ,  G11C13/02 ,  G11C17/16 ,  G11C17/18 ,  G11C2213/72 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An silver island anti-fuse including a first electrical conductor, an electrically resistive material in contact with the first conductor and at least one silver island disposed opposite the first electrical conductor and upon the electrically resistive material. A second electrical conductor disposed over the silver island intimately couples the silver island to the electrically resistive material. When a critical potential is applied across the anti-fuse, a metallic filament precipitates from the silver island through the electrically resistive material layer, establishing a short and thus switching the silver island anti-fuse from a high resistance to a low resistance. A method of making the silver island anti-fuse and a memory device incorporating the silver island anti-fuse are further provided.

摘要翻译： 一种银岛反熔丝，包括第一电导体，与第一导体接触的电阻材料和与第一电导体相对设置的至少一个银岛和电阻材料。 布置在银岛上的第二电导体将银岛紧密地耦合到电阻材料上。 当跨抗反熔丝施加临界电位时，金属细丝通过电阻材料层从银岛沉淀出来，建立短路，从而将银岛抗熔丝从高电阻切换到低电阻。 还提供了制造银岛反熔丝的方法和结合有银岛反熔丝的存储装置。

公开(公告)号：US20050176182A1

公开(公告)日：2005-08-11

申请号：US10777005

申请日：2004-02-10

申请人： Ping Me ,  Warren Jackson ,  Carl Taussig ,  Albert Jeans

发明人： Ping Me ,  Warren Jackson ,  Carl Taussig ,  Albert Jeans

IPC分类号： G03F7/20 ,  C23C16/00 ,  H01L21/00 ,  H01L21/027 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L51/00

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1292 ,  H01L29/66757 ,  H01L51/0097

摘要： An aspect of the present invention is a method for forming a plurality of thin-film devices. The method includes providing a flexible substrate and utilizing a self-aligned imprint lithography (SAIL) process to form the plurality of thin-film devices on the flexible substrate.

摘要翻译： 本发明的一个方面是形成多个薄膜器件的方法。 该方法包括提供柔性基板并利用自对准压印光刻（SAIL）工艺在柔性基板上形成多个薄膜器件。

公开(公告)号：US20050006640A1

公开(公告)日：2005-01-13

申请号：US10608791

申请日：2003-06-26

申请人： Warren Jackson ,  Sean Zhang ,  Craig Perlov

发明人： Warren Jackson ,  Sean Zhang ,  Craig Perlov

IPC分类号： G11C13/02 ,  H01L27/28 ,  H01L51/00 ,  H01L51/30 ,  H01L47/00

CPC分类号： G11C13/0016 ,  B82Y10/00 ,  G11C13/0014 ,  H01L27/28 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041

摘要： Fuse-type and antifuse-type semiconducting-organic-polymer-film-based memory elements for use in memory devices are disclosed. Various embodiments of the present invention employ a number of different techniques to alter the electrical conductance or, equivalently, the resistance, of organic-polymer-film memory elements in order to produce detectable memory-state changes in the memory elements. The techniques involve altering the electronic properties of the organic polymers by application of heat or electric fields, often in combination with additional chemical compounds, to either increase or decrease the resistance of the organic polymers.

摘要翻译： 公开了用于存储器件的保险丝型和反熔丝型半导体 - 有机聚合物膜基存储元件。 本发明的各种实施例使用多种不同的技术来改变有机 - 聚合物膜存储元件的电导率或等效的电阻，以便产生存储元件中的可检测的存储状态变化。 这些技术涉及通过施加热或电场（通常与其它化合物组合）来改变有机聚合物的电子性质来提高或降低有机聚合物的电阻。

公开(公告)号：US08097400B2

公开(公告)日：2012-01-17

申请号：US11062384

申请日：2005-02-22

申请人： Warren Jackson ,  Carl Taussig ,  Ping Mei

发明人： Warren Jackson ,  Carl Taussig ,  Ping Mei

IPC分类号： G03F7/20

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： Provided is a low cost system and method for forming electronic devices, especially large surface area devices. The process of imprint lithography is combined with alternate manufacturing techniques to fabricate the devices. Initially, a template imprints a three-dimensional pattern into a resist layer deposited on a flexible substrate. The resist layer is cured using ultraviolet light or other curing techniques. After curing, the 3-D pattern is modified using one of several techniques to include inkjetting, electrodeposition or laser patterning. In one embodiment, a semi-fluid material may be jetted into channels formed in the pattern, thereby forming conductive or insulating lead lines. Alternatively, a two-dimensional pattern may be jetted onto the resist layer. Final processing may include multiple etch-mask-etch steps. The integration of techniques into a single system provides a low cost, efficient method for manufacturing high quality, large surface area electronic devices.

摘要翻译： 提供一种用于形成电子装置，特别是大型表面积装置的低成本系统和方法。 压印光刻的过程与替代制造技术相结合以制造器件。 最初，模板将三维图案印刷到沉积在柔性基板上的抗蚀剂层中。 使用紫外线或其他固化技术固化抗蚀剂层。 固化后，使用几种技术之一来修改3-D图案，以包括喷墨，电沉积或激光图案化。 在一个实施例中，可以将半流体材料喷射到在图案中形成的通道中，从而形成导电或绝缘导线。 或者，可以将二维图案喷射到抗蚀剂层上。 最终处理可以包括多个蚀刻掩模蚀刻步骤。 将技术整合到单个系统中提供了用于制造高质量，大表面积电子器件的低成本，有效的方法。

公开(公告)号：US06980465B2

公开(公告)日：2005-12-27

申请号：US10739350

申请日：2003-12-19

申请人： Carl Taussig ,  Warren Jackson ,  Hao Luo

发明人： Carl Taussig ,  Warren Jackson ,  Hao Luo

IPC分类号： G11C17/14 ,  G11C5/02 ,  G11C7/00 ,  G11C8/00 ,  G11C8/10 ,  G11C11/00 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L27/10

CPC分类号： G11C17/16 ,  G11C5/025 ,  G11C8/10 ,  G11C13/0023 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： An addressing circuit is operable to address one or more memory elements in a cross-point memory array. The addressing circuit includes first and second sets of address lines for addressing the cross-point memory array. The address circuit also includes pull-up and pull-down circuit elements. Both the pull-up and pull-down circuit elements and the address lines include cross-point resistive elements.

摘要翻译： 寻址电路可操作以寻址交叉点存储器阵列中的一个或多个存储器元件。 寻址电路包括用于寻址交叉点存储器阵列的第一组地址线和第二组地址线。 地址电路还包括上拉和下拉电路元件。 上拉和下拉电路元件和地址线都包括交叉点电阻元件。

公开(公告)号：US20080100559A1

公开(公告)日：2008-05-01

申请号：US11590339

申请日：2006-10-30

申请人： Warren Jackson ,  Carl Taussig ,  Hao Luo

发明人： Warren Jackson ,  Carl Taussig ,  Hao Luo

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0254 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2320/043 ,  G09G2330/08

摘要： An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

摘要翻译： 描述了有源矩阵阵列内的集成线选择装置。 该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。 该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极， 通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

公开(公告)号：US20060188823A1

公开(公告)日：2006-08-24

申请号：US11062384

申请日：2005-02-22

申请人： Warren Jackson ,  Carl Taussig ,  Ping Mei

发明人： Warren Jackson ,  Carl Taussig ,  Ping Mei

IPC分类号： G03F7/00

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： Provided is a low cost system and method for forming electronic devices, especially large surface area devices. The process of imprint lithography is combined with alternate manufacturing techniques to fabricate the devices. Initially, a template imprints a three-dimensional pattern into a resist layer deposited on a flexible substrate. The resist layer is cured using ultraviolet light or other curing techniques. After curing, the 3-D pattern is modified using one of several techniques to include inkjetting, electrodeposition or laser patterning. In one embodiment, a semi-fluid material may be jetted into channels formed in the pattern, thereby forming conductive or insulating lead lines. Alternatively, a two-dimensional pattern may be jetted onto the resist layer. Final processing may include multiple etch-mask-etch steps. The integration of techniques into a single system provides a low cost, efficient method for manufacturing high quality, large surface area electronic devices.

摘要翻译： 提供一种用于形成电子装置，特别是大型表面积装置的低成本系统和方法。 压印光刻的过程与替代制造技术相结合以制造器件。 最初，模板将三维图案印刷到沉积在柔性基板上的抗蚀剂层中。 使用紫外线或其他固化技术固化抗蚀剂层。 固化后，使用几种技术之一来修改3-D图案，以包括喷墨，电沉积或激光图案化。 在一个实施例中，可以将半流体材料喷射到在图案中形成的通道中，从而形成导电或绝缘引线。 或者，可以将二维图案喷射到抗蚀剂层上。 最终处理可以包括多个蚀刻掩模蚀刻步骤。 将技术整合到单个系统中提供了用于制造高质量，大表面积电子器件的低成本，有效的方法。

公开(公告)号：US07817129B2

公开(公告)日：2010-10-19

申请号：US11590339

申请日：2006-10-30

申请人： Warren Jackson ,  Carl Taussig ,  Hao Luo

发明人： Warren Jackson ,  Carl Taussig ,  Hao Luo

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0254 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2320/043 ,  G09G2330/08

摘要： An integrated line selection apparatus within active matrix arrays is described. The circuit includes multiple gate line drive transistor devices, each gate line drive transistor device having a drain coupled to a gate line of multiple gate lines in a gate line driver circuit coupled to an active matrix array and a source to receive an input signal. The circuit further includes at least one address line transistor device corresponding to each gate line transistor device, each address line transistor device having a drain coupled to a gate of the corresponding gate line drive transistor device and a gate coupled to a corresponding address line, such that by asserting a predetermined combination of voltages on the plurality of address lines, a single gate line of said plurality of gate lines is selected to receive the input signal to be transmitted to a corresponding pixel within the corresponding active matrix array.

摘要翻译： 描述了有源矩阵阵列内的集成线选择装置。 该电路包括多个栅极线驱动晶体管器件，每个栅极线驱动晶体管器件具有耦合到耦合到有源矩阵阵列的栅极线驱动器电路中的多个栅极线的栅极线的漏极和用于接收输入信号的源极。 该电路还包括对应于每个栅极线晶体管器件的至少一个地址线晶体管器件，每个地址线晶体管器件具有耦合到相应的栅极线驱动晶体管器件的栅极的漏极和耦合到相应的地址线的栅极， 通过在多个地址线上确定电压的预定组合，选择所述多条栅极线的单个栅极线以接收要传输到相应的有源矩阵阵列内的对应像素的输入信号。

公开(公告)号：US20080100302A1

公开(公告)日：2008-05-01

申请号：US11590349

申请日：2006-10-30

申请人： Warren Jackson ,  Carl Taussig

发明人： Warren Jackson ,  Carl Taussig

IPC分类号： G01R31/08

CPC分类号： G01N27/221 ,  G01R31/2806

摘要： An apparatus and method for measuring and monitoring layer properties in web-based processes are described. The apparatus includes multiple electrode devices adjacently positioned on a surface of a web material, which advances with a predetermined speed. The electrode devices perform measurements of electrical parameters of a layer of the web material and provide an electrical signal to a layer deposition system for further adjustment of layer properties of the layer.

摘要翻译： 描述了一种用于在基于web的过程中测量和监测层属性的装置和方法。 该装置包括相邻地定位在幅材材料的表面上的多个电极装置，其以预定速度前进。 电极装置执行网状材料层的电参数的测量，并向层沉积系统提供电信号，以进一步调整层的层性质。

公开(公告)号：US08305096B2

公开(公告)日：2012-11-06

申请号：US11590349

申请日：2006-10-30

申请人： Warren Jackson ,  Carl Taussig

发明人： Warren Jackson ,  Carl Taussig

IPC分类号： G01R27/08

CPC分类号： G01N27/221 ,  G01R31/2806

摘要： An apparatus and method for measuring and monitoring layer properties in web-based processes are described. The apparatus includes multiple electrode devices adjacently positioned on a surface of a web material, which advances with a predetermined speed. The electrode devices perform measurements of electrical parameters of a layer of the web material and provide an electrical signal to a layer deposition system for further adjustment of layer properties of the layer.

摘要翻译： 描述了一种用于在基于web的过程中测量和监测层属性的装置和方法。 该装置包括相邻地定位在幅材材料的表面上的多个电极装置，其以预定速度前进。 电极装置执行网状材料层的电参数的测量，并向层沉积系统提供电信号，以进一步调整层的层性质。