公开(公告)号：US5627790A

公开(公告)日：1997-05-06

申请号：US408589

申请日：1995-03-22

申请人： Carla M. Golla ,  Marco Olivo ,  Silvia Padoan

发明人： Carla M. Golla ,  Marco Olivo ,  Silvia Padoan

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C7/02

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

摘要翻译： 一种包括通过选择电路连接到多个位线的负载的设备，以及连接到参考单元的负载，用于检测所选位线和参考单元中的电流。 连接到位线的负载包括晶体管，并且参考负载包括两个电流路径，每个由一个晶体管形成。 两个晶体管中的一个是二极管连接的，另一个晶体管可以由连接到相应晶体管的栅极端子的开关网络切换，以便在仅使能一个参考电流路径时将其关断，并且用于二极管连接 当两个参考电流路径都要使能时。

公开(公告)号：US5532972A

公开(公告)日：1996-07-02

申请号：US391920

申请日：1995-02-21

申请人： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

摘要翻译： 电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播 输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

公开(公告)号：US5748548A

公开(公告)日：1998-05-05

申请号：US711132

申请日：1996-09-09

申请人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

发明人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/407

CPC分类号： G11C5/143 ,  G11C16/30 ,  G11C5/147

摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

公开(公告)号：US5617356A

公开(公告)日：1997-04-01

申请号：US395361

申请日：1995-02-21

申请人： Carla Golla ,  Silvia Padoan ,  Marco Olivo

发明人： Carla Golla ,  Silvia Padoan ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16 ,  G11C16/02

CPC分类号： G11C16/16 ,  G11C16/14

摘要： A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.

摘要翻译： 一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关， 所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。 还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。 该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。

公开(公告)号：US5583820A

公开(公告)日：1996-12-10

申请号：US366211

申请日：1994-12-29

申请人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

发明人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/407

CPC分类号： G11C5/143 ,  G11C16/30 ,  G11C5/147

摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

摘要翻译： 一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。 比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。 稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。 电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。

公开(公告)号：US5600594A

公开(公告)日：1997-02-04

申请号：US412326

申请日：1995-03-31

申请人： Silvia Padoan ,  Marco Maccarrone ,  Marco Olivo

发明人： Silvia Padoan ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  G11C16/02

CPC分类号： G11C29/50004 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04

摘要： A circuit device for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier having a first input connected to a first circuit leg including at least one memory cell and a second input connected to a second or reference circuit leg, and circuit means effective to cause an unbalance in the values of the currents flowing in the reference leg. The device is connected between a first supply voltage reference and a second voltage reference, and said circuit means comprise a generator of a varying current as a function of the supply voltage which is associated with the reference leg.

摘要翻译： 一种用于测量电可编程，非易失性存储单元之间的阈值电压分布的电路装置，该装置包括差分放大器，该差分放大器具有连接到包括至少一个存储单元的第一电路支路的第一输入端和连接到第二或 参考电路支路和电路装置有效地引起在参考支路中流动的电流值的不平衡。 该设备连接在第一电源参考电压和第二参考电压之间，并且所述电路装置包括作为与参考支路相关联的电源电压的函数的变化电流的发电机。

公开(公告)号：US5519656A

公开(公告)日：1996-05-21

申请号：US366259

申请日：1994-12-29

申请人： Marco Maccarrone ,  Marco Olivo ,  Carla Golla ,  Silvia Padoan

发明人： Marco Maccarrone ,  Marco Olivo ,  Carla Golla ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/147

摘要： A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.

摘要翻译： 一种用于编程非易失性存储单元的电压调节器，其包括在第一和第二参考电压之间供电的放大器级，并且具有连接到第一参考电压的电阻分压器的第一输入端和反馈到所述第一参考电压的输出端 通过电流镜输入，源极跟随器晶体管由输出端控制，并通过编程线与单元连接。 还提供了连接到编程线的接地的MOS晶体管和连接在电流镜与第二参考电压之间的相应的电阻路径。

公开(公告)号：US5586077A

公开(公告)日：1996-12-17

申请号：US366212

申请日：1994-12-29

申请人： Marco Olivo ,  Silvia Padoan

发明人： Marco Olivo ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G06F1/24 ,  G11C16/06 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30

摘要： A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a supply voltage and a programming voltage, and a threshold detection circuit adapted to detect a decrease in the supply voltage, provides for the signal applied to the control logic to be obtained as a change-over function between the output signal from the threshold detector and a reset signal generated during the power-on transient of the device.

摘要翻译： 一种用于在电可编程非易失性存储装置中产生复位信号的方法，该方法包括存储单元矩阵和提供电源电压和编程电压的控制逻辑部分，以及阈值检测电路， 降低电源电压，提供作为在来自阈值检测器的输出信号与在器件的上电瞬变期间产生的复位信号之间的转换功能而获得的控制逻辑的信号。

公开(公告)号：US5644529A

公开(公告)日：1997-07-01

申请号：US635455

申请日：1996-04-18

申请人： Luigi Pascucci ,  Silvia Padoan

发明人： Luigi Pascucci ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C11/40

CPC分类号： G11C29/789 ,  G11C16/12 ,  G11C29/12

摘要： In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix. The switching means are controlled by a signal which determines the switching means to electrically connect the data electrode of the memory element to the address signal line when the memory cell of the non-volatile memory register is to be programmed, and to electrically disconnect the data electrode of the memory element from the address signal line when the information stored in the memory element is to be read by the load circuit.

摘要翻译： 在用于对与非易失性存储器寄存器用于存储冗余地址的存储器矩阵相关联的非易失性存储器寄存器中的存储器单元进行编程的集成电路中，存储器单元具有至少一个可编程非易失性存储器 元件具有控制电极和数据电极，并且适合于存储一位信息。 与存储器元件相关联的负载电路读取存储在其中的信息。 集成电路具有串联连接在数据电极和还提供存储器矩阵的解码电路的地址信号总线的相应地址信号线之间的开关装置。 开关装置由确定开关装置的信号控制，当非易失性存储寄存器的存储单元要被编程时，切换装置将存储元件的数据电极电连接到地址信号线，并且电连接数据 当存储在存储元件中的信息要由负载电路读取时，来自地址信号线的存储元件的电极。

公开(公告)号：US06392469B1

公开(公告)日：2002-05-21

申请号：US08347788

申请日：1994-11-30

申请人： Silvia Padoan ,  Carla Golla

发明人： Silvia Padoan ,  Carla Golla

IPC分类号： G05F110

CPC分类号： G05F3/245

摘要： A circuit for generating a stable reference voltage (Vref) as temperature and process parameters vary, including at least one field-effect transistor (M1) and an associated resistive bias element (R) connected in series between a supply voltage (Vcc) and ground (GND), further includes a second field-effect transistor (M2) connected to the first transistor such that the reference voltage (Vref) can be picked up as the difference between the respective threshold voltages of the two transistors. This provides a reference voltage which is uniquely stable against variations in temperature and process parameters.

摘要翻译： 用于产生作为温度和过程参数的稳定参考电压（Vref）的电路变化，包括串联连接在电源电压（Vcc）和地之间的至少一个场效应晶体管（M1）和相关联的电阻偏置元件（R） （GND），还包括连接到第一晶体管的第二场效应晶体管（M2），使得可以拾取参考电压（Vref）作为两个晶体管的各个阈值电压之间的差。 这提供了对温度和工艺参数变化独特稳定的参考电压。