公开(公告)号：US06292084B1

公开(公告)日：2001-09-18

申请号：US09136613

申请日：1998-08-20

申请人： Chang Auck Choi ,  Jong Hyun Lee ,  Won Ick Jang ,  Yong Il Lee ,  Jong Tae Baek ,  Hyung Joun Yoo

发明人： Chang Auck Choi ,  Jong Hyun Lee ,  Won Ick Jang ,  Yong Il Lee ,  Jong Tae Baek ,  Hyung Joun Yoo

IPC分类号： H01F500

CPC分类号： H01F5/003 ,  H01F17/0033

摘要： A fine inductor having a 3-dimensional coil structure is disclosed. The inductor includes an insulating layer having a groove, a plurality of first conductive patterns wherein the respective first conductive patterns cover bottom and both walls of the groove formed in the insulating layer, both ends of the respective first conductive patterns are extended over upper surface of both sides of the groove, and each of the first conductive patterns is disposed at a predetermined space between adjacent first conductive patterns, and a plurality of second conductive patterns wherein one ends of the respective second conductive patterns are connected to the one ends of the first conductive patterns extended over upper surface and the other ends of the respective second conductive patterns are connected to the other ends of the adjacent first conductive patterns extended over upper surface, thereby forming a coil structure together with the first conductive patterns.

摘要翻译： 公开了具有3维线圈结构的精细电感器。 电感器包括具有凹槽的绝缘层，多个第一导电图案，其中相应的第一导电图案覆盖形成在绝缘层中的凹槽的底部和两个壁，各个第一导电图案的两个端部延伸到 沟槽的两侧，并且每个第一导电图案设置在相邻的第一导电图案之间的预定空间处，以及多个第二导电图案，其中各个第二导电图案的一端连接到第一导电图案的一端 在上表面延伸的导电图案和相应的第二导电图案的另一端连接到在上表面上延伸的相邻的第一导电图案的另一端，从而与第一导电图案一起形成线圈结构。

公开(公告)号：US6084656A

公开(公告)日：2000-07-04

申请号：US141554

申请日：1998-08-28

申请人： Chang Auck Choi ,  Jong Hyun Lee ,  Won Ick Jang ,  Yong Il Lee ,  Jong Tae Baek ,  Bo Woo Kim

发明人： Chang Auck Choi ,  Jong Hyun Lee ,  Won Ick Jang ,  Yong Il Lee ,  Jong Tae Baek ,  Bo Woo Kim

IPC分类号： G03F7/20 ,  G03B27/72 ,  G03B27/42 ,  G03F9/00

CPC分类号： G03F7/70291

摘要： This invention discloses a programmable mask for exposure apparatus which is formed by an integrated pixels of a micro-devices which shut or open a light by an electrical signal. This invention provides a photolithography method by projecting on a silicon wafer a directly designed circuit pattern which is made on a programmable mask fabricated by an integration of many a micro optical shutter devices as a pixels.

摘要翻译： 本发明公开了一种曝光装置的可编程掩模，其由通过电信号关闭或打开光的微器件的集成像素形成。 本发明提供了一种通过在硅晶片上投影直接设计的电路图案的光刻方法，该电路图案是通过将许多微型光学快门器件集成为像素而制造的可编程掩模上制成的。

公开(公告)号：US06225145B1

公开(公告)日：2001-05-01

申请号：US09390850

申请日：1999-09-07

申请人： Chang Auck Choi ,  Jong Hyun Lee ,  Won Ick Jang ,  Dae Yong Kim

发明人： Chang Auck Choi ,  Jong Hyun Lee ,  Won Ick Jang ,  Dae Yong Kim

IPC分类号： H01L2144

CPC分类号： B81C1/00301 ,  B81B2207/096 ,  H01L21/76838 ,  H01L2224/48465 ,  H01L2924/10253 ,  H01L2924/00

摘要： Provided is a method of fabricating a vacuum micro-structure, which is used for an element operating in a vacuum, the method comprising the steps of: (1) entirely etching an epitaxial layer of a silicon substrate having an SOI structure including an upper silicon epitaxial layer, an interlevel insulating layer and a lower silicon bulk layer to form two electrode structures and a floating vibratory structure, and encapsulating them with a vacuum sealing substrate in a vacuum; and (2) etching the silicon substrate having the SOI stricture from the back side to the interlevel insulating layer to open the electrode structures, and forming a metal electrode.

摘要翻译： 提供一种制造真空微结构的方法，其用于在真空中操作的元件，所述方法包括以下步骤：（1）完全蚀刻具有SOI结构的硅衬底的外延层，所述SOI衬底包括上硅 外延层，层间绝缘层和下硅体层，以形成两个电极结构和浮动振动结构，并在真空中用真空密封基板封装它们; 以及（2）从背面蚀刻具有SOI限制的硅衬底到层间绝缘层，以打开电极结构，以及形成金属电极。

公开(公告)号：US06342427B1

公开(公告)日：2002-01-29

申请号：US09473968

申请日：1999-12-29

申请人： Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

发明人： Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

IPC分类号： H01L2100

CPC分类号： B81C1/00047 ,  B81B2203/033 ,  B81C2201/0133 ,  B81C2201/0178 ,  B81C2203/0136

摘要： A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

摘要翻译： 公开了一种用于形成微腔的方法。 在形成空腔的方法中，在硅层上形成第一层，并且通过选择性地蚀刻硅层，在硅层中形成沟槽。 在沟槽和硅层上形成第二和第三层。 通过部分地蚀刻第三层，通过第三层形成蚀刻孔。 在通过蚀刻孔除去第二层之后，在硅层和第三层之间形成空穴。 因此，通过利用硅或多晶硅层的体积膨胀，可以容易地在硅层中形成并密封具有大尺寸的空腔。 此外，可以根据在热氧化处理后部分打开的蚀刻孔上形成的低真空CVD氧化物层或氮化物层，通过控制与聚合物的其它部分相关的蚀刻孔的尺寸，形成真空微腔 硅层。

公开(公告)号：US20100009514A1

公开(公告)日：2010-01-14

申请号：US12417114

申请日：2009-04-02

申请人： Myung Lae LEE ,  Jong Hyun Lee ,  Sung Sik Yun ,  Dae Hun Jeong ,  Gunn Hwang ,  Chang Auck Choi ,  Chang Han Je ,  Jae Yong An

发明人： Myung Lae LEE ,  Jong Hyun Lee ,  Sung Sik Yun ,  Dae Hun Jeong ,  Gunn Hwang ,  Chang Auck Choi ,  Chang Han Je ,  Jae Yong An

IPC分类号： H01L21/306

CPC分类号： B81C1/00619 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0133

摘要： A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.

摘要翻译： 提供一种制造微垂直结构的方法。 该方法包括通过插入绝缘层图案和空腔将第二晶体硅（Si）衬底接合到第一晶体Si衬底上，使用沿[111]晶体的深反应离子蚀刻（DRIE）工艺蚀刻第二晶体Si衬底 垂直于第二晶体Si衬底，并且使用结晶湿蚀刻工艺蚀刻第二晶体Si衬底的蚀刻垂直表面，以改善蚀刻垂直表面的表面粗糙度和平坦度。 结果，蚀刻的垂直表面上没有形成形态缺陷。 此外，由于绝缘层图案，在蚀刻终点处不发生基脚。 此外，微垂直结构不会浮在空气中，而是固定在第一晶体Si衬底上，从而有助于后续工艺。

公开(公告)号：US07745308B2

公开(公告)日：2010-06-29

申请号：US12417114

申请日：2009-04-02

申请人： Myung Lae Lee ,  Jong Hyun Lee ,  Sung Sik Yun ,  Dae Hun Jeong ,  Gunn Hwang ,  Chang Auck Choi ,  Chang Han Je ,  Jae Yong An

发明人： Myung Lae Lee ,  Jong Hyun Lee ,  Sung Sik Yun ,  Dae Hun Jeong ,  Gunn Hwang ,  Chang Auck Choi ,  Chang Han Je ,  Jae Yong An

IPC分类号： H01L21/00

CPC分类号： B81C1/00619 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0133

摘要： A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.

摘要翻译： 提供一种制造微垂直结构的方法。 该方法包括通过插入绝缘层图案和空腔将第二晶体硅（Si）衬底接合到第一晶体Si衬底上，使用沿[111]晶体的深反应离子蚀刻（DRIE）工艺蚀刻第二晶体Si衬底 垂直于第二晶体Si衬底，并且使用结晶湿蚀刻工艺蚀刻第二晶体Si衬底的蚀刻垂直表面，以改善蚀刻垂直表面的表面粗糙度和平坦度。 结果，蚀刻的垂直表面上没有形成形态缺陷。 此外，由于绝缘层图案，在蚀刻终点处不发生基脚。 此外，微垂直结构不会浮在空气中，而是固定在第一晶体Si衬底上，从而有助于后续工艺。

公开(公告)号：US08261617B2

公开(公告)日：2012-09-11

申请号：US12745745

申请日：2008-04-21

申请人： Chang Auck Choi ,  Chang Han Je ,  Gunn Hwang ,  Youn Tae Kim ,  Sung Hae Jung ,  Myung Lae Lee ,  Sung Sik Lee ,  Seok Hwan Moon

发明人： Chang Auck Choi ,  Chang Han Je ,  Gunn Hwang ,  Youn Tae Kim ,  Sung Hae Jung ,  Myung Lae Lee ,  Sung Sik Lee ,  Seok Hwan Moon

IPC分类号： G01L9/06 ,  B23P17/04

CPC分类号： G01L9/0042 ,  Y10T29/42 ,  Y10T29/49

摘要： A micro semiconductor-type pressure sensor and a manufacturing method thereof are provided. The micro semi-conductor-type pressure sensor is implemented by etching a cavity-formation region of a substrate to form a plurality of trenches, oxidizing the plurality of trenches through a thermal oxidation process to form a cavity-formation oxide layer, forming a membrane-formation material layer on upper portions of the cavity-formation oxide layer and the substrate, forming a plurality of etching holes in the membrane-formation material layer, removing the cavity-formation oxide layer through the plurality of etching holes to form a cavity buried in the substrate, forming a membrane reinforcing layer on an upper portion of the membrane-formation material layer to form a membrane for closing the cavity, and forming sensitive films made of a piezoresisive material on an upper portion of the membrane.

摘要翻译： 提供一种微型半导体型压力传感器及其制造方法。 微型半导体型压力传感器通过蚀刻衬底的空腔形成区域以形成多个沟槽来实现，通过热氧化工艺氧化多个沟槽以形成空腔形成氧化物层，形成膜 在形成空腔的氧化物层和衬底的上部上形成一层形成材料层，在膜形成材料层中形成多个蚀刻孔，通过多个蚀刻孔去除腔形成氧化物层，以形成埋入腔 在所述基板中，在所述膜形成材料层的上部形成膜增强层，以形成用于封闭所述空腔的膜，并且在所述膜的上部形成由压阻材料制成的敏感膜。

公开(公告)号：US08143579B2

公开(公告)日：2012-03-27

申请号：US12859466

申请日：2010-08-19

申请人： Woo Seok Yang ,  Sang Hoon Cheon ,  Seong Mok Cho ,  Ho Jun Ryu ,  Chang Auck Choi

发明人： Woo Seok Yang ,  Sang Hoon Cheon ,  Seong Mok Cho ,  Ho Jun Ryu ,  Chang Auck Choi

IPC分类号： G01J5/20

CPC分类号： G01J5/04 ,  G01J5/046

摘要： A resistive material for a bolometer, a bolometer for an infrared detector using the material, and a method of manufacturing the bolometer are provided. In the resistive material, at least one element selected from the group consisting of nitrogen (N), oxygen (O) and germanium (Ge) is included in antimony (Sb). The resistive material has superior properties such as high temperature coefficient of resistance (TCR), low resistivity, a low noise constant, and is easily formed in a thin film structure by sputtering typically used in a complementary metal-oxide semiconductor (CMOS) process, so that it can be used as a resistor for the bolometer for an uncooled infrared detector, and thus provide the infrared detector with superior temperature precision.

摘要翻译： 提供了用于测辐射热力计的电阻材料，用于使用该材料的红外探测器的测辐射热计，以及制造测辐射热计的方法。 在电阻材料中，选自氮（N），氧（O）和锗（Ge）中的至少一种元素包括在锑（Sb）中。 电阻材料具有优异的性能，例如高温电阻系数（TCR），低电阻率，低噪声常数，并且易于通过通常用于互补金属氧化物半导体（CMOS）工艺中的溅射在薄膜结构中形成， 因此它可以用作非制冷红外探测器的辐射热计的电阻器，从而为红外检测器提供出色的温度精度。

公开(公告)号：US20090308160A1

公开(公告)日：2009-12-17

申请号：US12355644

申请日：2009-01-16

申请人： Chang Han Je ,  Chang Kyu Kim ,  Chang Auck Choi

发明人： Chang Han Je ,  Chang Kyu Kim ,  Chang Auck Choi

IPC分类号： G01P15/125

CPC分类号： G01P15/125

摘要： Provided is a vertical acceleration measuring apparatus including a substrate; a plumb that is separated from the substrate to operate; a plurality of movable electrode plates that are formed at an upper end of the plumb in a predetermined direction; a movable electrode plate supporting portion that is formed at the upper end of the plumb and supports the movable electrode plates; a fixed body that is formed at an upper end of the substrate; a fixed electrode plate supporting portion that is coupled to the fixed body adjacent to the upper end of the plumb; a plurality of fixed electrode plates that are supported by the fixed electrode plate supporting portion and arranged to face the movable electrode plates in parallel; and a connection spring that connects the fixed body and the movable electrode plate supporting portion.

摘要翻译： 提供一种包括基板的垂直加速度测量装置; 与基板分离的铅垂操作; 多个可动电极板，其沿预定方向形成在铅垂的上端; 可动电极板支撑部分，其形成在铅垂的上端并支撑可动电极板; 形成在所述基板的上端的固定体; 固定电极板支撑部，其与所述固定体联接，所述固定体邻近所述铅垂的上端; 多个固定电极板，由固定电极板支撑部支撑并平行地面对可动电极板; 以及连接固定体和可动电极板支撑部的连接弹簧。

公开(公告)号：US07012752B2

公开(公告)日：2006-03-14

申请号：US11045554

申请日：2005-01-27

申请人： Chang Auck Choi ,  Myung Lae Lee ,  Chang Kyu Kim ,  Chi Hoon Jun ,  Youn Tae Kim

发明人： Chang Auck Choi ,  Myung Lae Lee ,  Chang Kyu Kim ,  Chi Hoon Jun ,  Youn Tae Kim

IPC分类号： G02B27/00

CPC分类号： G02B26/001 ,  G01J3/26 ,  G02B5/0833 ,  G02B6/29361 ,  G02B6/29389 ,  G02B6/29395

摘要： An active type tunable wavelength optical filter having a Fabry-Perot structure is disclosed. A tunable wavelength optical filter which comprises a lower mirror in which silicon films and oxide films are sequentially laminated in a multi-layer and the silicon film is laminated on the highest portion; an upper mirror in which silicon films and oxide films are sequentially laminated in a multi-layer and the silicon film is laminated on the highest portion and which is spaced away from the lower mirror by a predetermined distance; a connecting means for connecting and supporting the lower mirror and the upper mirror to a semiconductor substrate; and electrode pads for controlling the gap between the lower mirror and the upper mirror by an electrostatic force and the method of manufacturing the same are provided. Thereby, by finely driving the upper and lower mirrors composed of a multi-layer structure of the silicon film and the oxide film by the electrostatic force, the wavelength of the transmitted light with respect to the incident light can be selectively sent.

摘要翻译： 公开了一种具有法布里 - 珀罗结构的有源型可调谐波长滤光器。 一种可调波长滤光器，包括下反射镜，其中硅膜和氧化物膜顺次层叠在多层中，并且硅膜层压在最高部分上; 其中硅膜和氧化物膜顺次层叠在多层中并且硅膜层压在最高部分上并且与下反射镜间隔预定距离的上反射镜; 用于将下反射镜和上反射镜连接和支撑到半导体基板的连接装置; 以及用于通过静电力控制下反射镜和上反射镜之间的间隙的电极焊盘及其制造方法。 由此，通过利用静电力微细地驱动由硅膜和氧化膜构成的上反射镜和下反射镜，可以选择性地发送透射光相对于入射光的波长。