公开(公告)号：US20100163825A1

公开(公告)日：2010-07-01

申请号：US12346507

申请日：2008-12-30

申请人： Charles H. Dennison ,  George A. Gordon ,  John M. Peters

发明人： Charles H. Dennison ,  George A. Gordon ,  John M. Peters

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

摘要： A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.

摘要翻译： 相变存储单元可以由被击穿层分开的一对硫族化物相变层形成。 在使用存储器之前可以将击穿层分解，使得在击穿层内限定导电击穿点。 在某些情况下，故障点可能与周围大气良好隔离，减少热损失和降低电流消耗。 此外，在某些情况下，击穿点可能与上覆电极和下层电极很好地隔离，从而减少与污染有关的问题。 击穿点可以放置在一对硫族化物层之间，其中两个硫族化物层的电极出发。

公开(公告)号：US20070279974A1

公开(公告)日：2007-12-06

申请号：US11447819

申请日：2006-06-06

申请人： Charles H. Dennison ,  John M. Peters

发明人： Charles H. Dennison ,  John M. Peters

IPC分类号： G11C11/00 ,  H01L23/58

CPC分类号： G11C11/00 ,  G11C13/0004 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

摘要： Rather than depositing a heater material into a pore, a heater material may be first blanket deposited over a select device. The heater material may then be covered by a mask, such that the mask and the heater material may be etched to form a stack. Then, the region between adjacent stacks that form separate cells may be filled with an insulator. After removing the mask material, a pore is then formed in the insulator over the heater. This may then be filled with chalcogenide to form a phase change memory.

摘要翻译： 不是将加热器材料沉积到孔中，加热器材料可以首先被覆盖地沉积在选择装置上。 加热器材料然后可以被掩模覆盖，使得掩模和加热器材料可以被蚀刻以形成堆叠。 然后，可以用绝缘体填充形成分离单元的相邻叠层之间的区域。 在去除掩模材料之后，在加热器上的绝缘体中形成孔。 然后可以用硫属化物填充，以形成相变记忆。

公开(公告)号：US08462545B2

公开(公告)日：2013-06-11

申请号：US13526686

申请日：2012-06-19

申请人： Charles H. Dennison ,  Stephen J. Hudgens

发明人： Charles H. Dennison ,  Stephen J. Hudgens

IPC分类号： G11C11/00

CPC分类号： H01L45/065 ,  G11C13/0004 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  Y10S977/754

摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

公开(公告)号：US20120081956A1

公开(公告)日：2012-04-05

申请号：US13315374

申请日：2011-12-09

申请人： Charles H. Dennison ,  Stephen J. Hudgens

发明人： Charles H. Dennison ,  Stephen J. Hudgens

IPC分类号： G11C11/00

CPC分类号： H01L45/065 ,  G11C13/0004 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  Y10S977/754

摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

摘要翻译： 根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。 这可能会降低所得相变存储器的功耗。 功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。 例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。 在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

公开(公告)号：US20100200829A1

公开(公告)日：2010-08-12

申请号：US12764157

申请日：2010-04-21

申请人： Charles H. Dennison ,  Stephen J. Hudgens

发明人： Charles H. Dennison ,  Stephen J. Hudgens

IPC分类号： H01L45/00

CPC分类号： H01L45/065 ,  G11C13/0004 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  Y10S977/754

摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.

摘要翻译： 根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。 这可能会降低所得相变存储器的功耗。 功耗的降低可以通过在编程体积之外形成很少或不混合的不同的相变材料层来实现。 例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。 在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

公开(公告)号：US20080177943A1

公开(公告)日：2008-07-24

申请号：US12069812

申请日：2008-02-12

申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

公开(公告)号：US07390691B2

公开(公告)日：2008-06-24

申请号：US11262250

申请日：2005-10-28

申请人： Charles H. Dennison ,  Ilya V. Karpov

发明人： Charles H. Dennison ,  Ilya V. Karpov

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1675

摘要： A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does not. In another approach, a hard mask is used which is of substantially the same material as an overlying and surrounding insulator. The hard mask and an underlying phase change material are protected by a sidewall spacer of a different material than the hard mask. If the hard mask and the insulator have substantially the same etch characteristics, the hard mask may be removed while maintaining the protective character of the sidewall spacer.

摘要翻译： 可以形成具有较高列着陆边缘的相变存储器。 在一种方法中，可以通过增加电极的高度来增加列着色边缘。 例如，电极由两种不同的材料制成，其中之一包括氮化物，另一个不包括氮化物。 在另一种方法中，使用与覆盖和围绕的绝缘体基本上相同的材料的硬掩模。 硬掩模和下面的相变材料由与硬掩模不同的材料的侧壁间隔物保护。 如果硬掩模和绝缘体具有基本相同的蚀刻特性，则可以去除硬掩模，同时保持侧壁间隔物的保护特性。

公开(公告)号：US07315082B2

公开(公告)日：2008-01-01

申请号：US10443471

申请日：2003-05-22

申请人： Charles H. Dennison ,  Trung T. Doan

发明人： Charles H. Dennison ,  Trung T. Doan

IPC分类号： H01L23/48

CPC分类号： H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

摘要翻译： 公开了一种用于在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间，可以重复上述过程一次或多次。

公开(公告)号：US07064036B2

公开(公告)日：2006-06-20

申请号：US10932192

申请日：2004-09-01

申请人： John K. Zahurak ,  Brent Keeth ,  Charles H. Dennison

发明人： John K. Zahurak ,  Brent Keeth ,  Charles H. Dennison

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78648

摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.

摘要翻译： 根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。 这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。 绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

公开(公告)号：US06919578B2

公开(公告)日：2005-07-19

申请号：US10313785

申请日：2002-12-06

申请人： Tyler A. Lowrey ,  Charles H. Dennison

发明人： Tyler A. Lowrey ,  Charles H. Dennison

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L27/24 ,  H01L47/00

CPC分类号： H01L21/7685 ,  H01L21/28562 ,  H01L21/76888 ,  H01L27/24

摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.