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    Computer address modification system using writable mapping and page stores
    5.
    发明授权
    Computer address modification system using writable mapping and page stores 失效
    使用可写映射和页面存储的计算机地址修改系统

    公开(公告)号：US5101339A

    公开(公告)日：1992-03-31

    申请号：US300560

    申请日：1989-01-23

    申请人： Bruce A. Fairman ,  Allen J. Larsen ,  William G. Swinton ,  Robert G. Taylor, Jr.

    发明人： Bruce A. Fairman ,  Allen J. Larsen ,  William G. Swinton ,  Robert G. Taylor, Jr.

    IPC分类号： G06F12/06 ,  G06F12/10

    CPC分类号： G06F12/0623 ,  G06F12/1081

    摘要： A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA addresses which may match the 16 K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

    摘要翻译： 计算机系统包括计算机地址修改系统，其有利地耦合在总线网络中以选择性地转换16K个块中的存储器地址数据，并提供可匹配16K个存储器地址块的DMA地址。 修改系统包括映射RAM，其选择性地提供翻译的地址以使得能够在16兆字节扩展地址空间中的地址。 该修改系统还包括一页面寄存器，用于存储针对每个DMA通道的每个可寻址的16K数据块，扩展地址空间内的页地址。

    Computer address modification system with optional DMA paging
    6.
    发明授权
    Computer address modification system with optional DMA paging 失效
    具有可选DMA寻呼功能的计算机地址修改系统

    公开(公告)号：US4849875A

    公开(公告)日：1989-07-18

    申请号：US84318

    申请日：1987-08-10

    申请人： Bruce A. Fairman ,  Allen J. Larsen ,  William G. Swinton ,  Robert G. Taylor, Jr.

    发明人： Bruce A. Fairman ,  Allen J. Larsen ,  William G. Swinton ,  Robert G. Taylor, Jr.

    IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  G06F13/32

    CPC分类号： G06F12/0623 ,  G06F12/0292 ,  G06F13/32 ,  G06F12/1081 ,  G06F2212/206

    摘要： A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA page addresses in 16K blocks which may match the 16K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

    摘要翻译： 计算机系统包括有利地耦合在总线网络中的计算机地址修改系统，以选择性地转换16K个块中的存储器地址数据，并在16K个块中提供与16K个存储器地址块匹配的DMA页地址。 修改系统包括映射RAM，其选择性地提供翻译的地址以使得能够在16兆字节扩展地址空间中的地址。 该修改系统还包括一页面寄存器，用于存储针对每个DMA通道的每个可寻址的16K数据块，扩展地址空间内的页地址。

    Method of and apparatus for dispatching a processing element to a program location based on channel number of received data
    7.
    发明授权
    Method of and apparatus for dispatching a processing element to a program location based on channel number of received data 有权
    基于接收到的数据的频道号将处理元件发送到节目位置的方法和装置

    公开(公告)号：US6167471A

    公开(公告)日：2000-12-26

    申请号：US172994

    申请日：1998-10-14

    申请人： Jung-Jen Liu ,  Bruce A. Fairman

    发明人： Jung-Jen Liu ,  Bruce A. Fairman

    IPC分类号： G06F13/12 ,  H04L12/28 ,  H04L12/56 ,  G06F13/10 ,  G06F9/30 ,  G11C8/00 ,  H04J3/26

    CPC分类号： H04L49/90

    摘要： An apparatus for dispatching a processing element to a program location based on a channel number of received data includes a channel pointer register having a number of storage locations each with a channel number field, a valid bit field and a corresponding instruction pointer field. When an isochronous channel is allocated for use for reception, the host device programs the channel number and a corresponding instruction pointer value into a storage location. When a storage location is programmed, a valid bit within that storage location is also preferably set. The corresponding instruction pointer value points to a series of instructions which are to be used to process data received on that isochronous channel. When isochronous data is then received, the channel number on which the data is received is compared to the channel numbers within the valid storage locations in the channel pointer register. If one of the channel numbers within a valid storage location matches the channel number of the received data, then the corresponding instruction pointer value is output and the data is processed according to a series of instructions beginning at the location specified by the corresponding instruction pointer value. Otherwise, if the channel number of the received data does not match any of the channel numbers within valid storage locations then a default instruction pointer value is output and the received data is processed according to a series of instructions beginning at the location specified by the default instruction pointer value.

    摘要翻译： 一种用于基于接收数据的频道号将处理元件分配到节目位置的装置包括具有多个存储位置的频道指针寄存器，每个存储位置具有频道号字段，有效位字段和相应的指令指针字段。 当同步信道被分配用于接收时，主机设备将信道号和相应的指令指针值编程到存储位置。 当存储位置被编程时，也优选地设置该存储位置内的有效位。 相应的指令指针值指向要用于处理在同步信道上接收的数据的一系列指令。 当接收到等时数据时，将接收数据的通道号与通道指针寄存器中的有效存储位置内的通道号进行比较。 如果有效存储位置中的一个通道号与接收到的数据的通道号匹配，则输出相应的指令指针值，并根据从相应指令指针值指定的位置开始的一系列指令来处理数据 。 否则，如果接收到的数据的通道号与有效存储位置内的任何通道号不匹配，则输出默认指令指针值，并根据从默认值指定的位置开始的一系列指令来处理接收到的数据 指令指针值。

    Method for implementing scheduling mechanisms with selectable resource modes
    9.
    发明授权
    Method for implementing scheduling mechanisms with selectable resource modes 有权
    用可选资源模式实现调度机制的方法

    公开(公告)号：US06453376B1

    公开(公告)日：2002-09-17

    申请号：US09521334

    申请日：2000-03-09

    申请人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

    发明人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

    IPC分类号： G06F1200

    CPC分类号： G06F9/485 ,  G06F9/4881 ,  G06F2209/485

    摘要： A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

    摘要翻译： 用于用可选资源模式实现调度机制的方法包括至少一个资源表征集合，其包括多个资源表征，每个资源表征都具有用于执行所请求的进程的资源需求。 多个资源表征可以包括大多数模式，最佳模式和最差模式。 然后，分配管理器可以选择资源模式，并将所请求进程的相应资源需求与当前可用的设备资源进行比较。 然后，分配管理器可以根据当前可用的资源是否足以充分地满足所请求进程的资源需求来授权或拒绝所请求的进程。

    System and method for multi-level context switching in an electronic network
    10.
    发明授权
    System and method for multi-level context switching in an electronic network 有权
    电子网络多层次上下文切换的系统和方法

    公开(公告)号：US06169745A

    公开(公告)日：2001-01-02

    申请号：US09336064

    申请日：1999-06-18

    申请人： Jung-Jen Liu ,  Scott Smyers ,  Bruce A. Fairman ,  Steve Pham ,  Jose L. Diaz ,  Richard A. Bardini

    发明人： Jung-Jen Liu ,  Scott Smyers ,  Bruce A. Fairman ,  Steve Pham ,  Jose L. Diaz ,  Richard A. Bardini

    IPC分类号： G06F1334

    CPC分类号： H04L12/40058 ,  G06F9/3806 ,  G06F9/4486

    摘要： A system and method for multi-level context switching in an electronic network comprises a control state machine configured to implement a data priority scheme, a return address generator configured to hold and release return addresses for interrupted instruction modules in accordance with the data priority scheme and context information from the electronic network, and a processor configured to process data from the electronic network in accordance with the data priority scheme and the context information. Receive registers stores data received from the electronic network. The control state machine includes a switch address generator and a program counter select. The switch address generator outputs a switch address, which is an address for a first instruction for a selected-context instruction module. The return address generator holds and releases the return addresses, which are addresses of next consecutive instructions, when an instruction module is interrupted for a context switch. The program counter select outputs a switch address, a return address, or a next consecutive address to select the appropriate instruction in the memory for execution by the processor.

    摘要翻译： 一种用于电子网络中的多级上下文切换的系统和方法，包括配置成实现数据优先方案的控制状态机，被配置为根据数据优先级方案保存和释放中断的指令模块的返回地址的返回地址发生器，以及 来自电子网络的上下文信息，以及被配置为根据数据优先级方案和上下文信息来处理来自电子网络的数据的处理器。 接收寄存器存储从电子网络接收的数据。 控制状态机包括切换地址发生器和程序计数器选择。 开关地址产生器输出开关地址，该开关地址是用于所选上下文指令模块的第一指令的地址。 返回地址生成器保存并释放当上下文切换中断指令模块时的返回地址，后者是下一个连续指令的地址。 程序计数器选择输出开关地址，返回地址或下一个连续地址，以选择存储器中适当的指令以供处理器执行。