公开(公告)号：US07602265B2

公开(公告)日：2009-10-13

申请号：US11163485

申请日：2005-10-20

申请人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

发明人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

IPC分类号： H01H51/22

CPC分类号： H01H59/0009

摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。

公开(公告)号：US09043179B2

公开(公告)日：2015-05-26

申请号：US12985443

申请日：2011-01-06

申请人： Charles J. Montrose ,  Ping-Chuan Wang

发明人： Charles J. Montrose ,  Ping-Chuan Wang

IPC分类号： G01R31/00 ,  G01R31/14 ,  G01R31/319 ,  G01R31/3193

CPC分类号： G01R31/2834 ,  G01R31/2607 ,  G01R31/2851 ,  G01R31/31924 ,  G01R31/31935

摘要： A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.

摘要翻译： 一种用于测试晶片上的多个晶体管的系统，具有经由总线连接到多个驱动器的存储装置或个人计算机。 每个电压驱动器具有微控制器，其适于接收测试参数并从多个电压驱动器提供测试数据。 通过利用总线结构，个人计算机可以在一个总线上查看标志，指示测试数据可从驱动器获得并接收数据。 此外，还可以使用总线为驱动程序提供测试参数。 以这种方式，可以同时运行多个驱动程序并入多个测试。 当数据可用时，它被传送到个人计算机，用于向多个驱动器提供测试参数，并且经由第二总线连接以从多个驱动器接收测试结果。

公开(公告)号：US20120179409A1

公开(公告)日：2012-07-12

申请号：US12985443

申请日：2011-01-06

申请人： Charles J. Montrose ,  Ping-Chuan Wang

发明人： Charles J. Montrose ,  Ping-Chuan Wang

IPC分类号： G06F19/00

CPC分类号： G01R31/2834 ,  G01R31/2607 ,  G01R31/2851 ,  G01R31/31924 ,  G01R31/31935

摘要： A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.

摘要翻译： 一种用于测试晶片上的多个晶体管的系统，具有经由总线连接到多个驱动器的存储装置或个人计算机。 每个电压驱动器具有微控制器，其适于接收测试参数并从多个电压驱动器提供测试数据。 通过利用总线结构，个人计算机可以在一个总线上查看标志，指示测试数据可从驱动器获得并接收数据。 此外，还可以使用总线为驱动程序提供测试参数。 以这种方式，可以同时运行多个驱动程序并入多个测试。 当数据可用时，它被传送到个人计算机，用于向多个驱动器提供测试参数，并且经由第二总线连接以从多个驱动器接收测试结果。

公开(公告)号：US20120179943A1

公开(公告)日：2012-07-12

申请号：US12985459

申请日：2011-01-06

申请人： Charles J. Montrose ,  Ping-Chuan Wang

发明人： Charles J. Montrose ,  Ping-Chuan Wang

IPC分类号： G11C29/08 ,  G06F11/26

CPC分类号： G06F11/2273 ,  G11C29/006 ,  G11C29/06 ,  G11C29/56 ,  G11C2029/5602

摘要： A method for transmitting data from test device to a storage device via a parallel bus. The methods comprising the steps of setting a flag to indicate that data is available, reading the data, setting a flag to indicate the data was read. In addition test parameters are sent to the test device from the storage device, the method comprises the steps of checking to see if a test device is ready to receive data, transferring the test parameters, identifying the next channel to update.

摘要翻译： 一种通过并行总线从测试设备向存储设备发送数据的方法。 所述方法包括以下步骤：设置标志以指示数据可用，读取数据，设置用于指示数据的标志。 此外，测试参数从存储设备发送到测试设备，该方法包括检查测试设备是否准备好接收数据，传送测试参数，识别下一个信道进行更新的步骤。

公开(公告)号：US06940285B2

公开(公告)日：2005-09-06

申请号：US10250272

申请日：2003-06-19

申请人： Charles J. Montrose ,  Ping-Chuan Wang

发明人： Charles J. Montrose ,  Ping-Chuan Wang

IPC分类号： G01R31/02 ,  G01R31/327 ,  H01H11/00 ,  H01H59/00

CPC分类号： H01H11/0062 ,  B81C99/005 ,  H01H59/0009

摘要： A system and method for testing performance characteristics of a MEMs device includes an activation driver configured to receive and drive a waveform to an activation side of the micro electromechanical device and configured to provide readback of an activation voltage and activation current drawn by activation of the micro electromechanical device. A switch driver configured to provide a load to a switch side of the micro electromechanical device provides readback of a load voltage and a load current drawn by the micro electromechanical device. A contact-closure counter and master control card (MCC) is included to control the activation and switch drivers while a digital volt meter (DVM) is in operable communication with the micro electromechanical device to read back analog readback. An analog multiplexer provides the analog readback to a corresponding activation driver or switch driver. A computer having software provides system control, data acquisition, data storage, and data analysis is in operable communication with the multiplexer, DVM and MCC.

摘要翻译： 用于测试MEMs器件的性能特性的系统和方法包括激活驱动器，其被配置为接收并驱动波形到微机电装置的激活侧，并且被配置为提供激活电压的读回和通过激活微机 机电装置。 配置为向微机电装置的开关侧提供负载的开关驱动器提供对由微机电装置吸取的负载电压和负载电流的回读。 包括触点闭合计数器和主控卡（MCC）以控制激活和切换驱动器，而数字电压表（DVM）可与微机电装置可操作地通信以读回模拟回读。 模拟多路复用器将模拟回读提供给相应的激活驱动器或开关驱动器。 具有软件的计算机提供系统控制，数据采集，数据存储和数据分析与多路复用器DVM和MCC可操作地通信。

公开(公告)号：US08853693B2

公开(公告)日：2014-10-07

申请号：US13423823

申请日：2012-03-19

申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L21/76898

摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

公开(公告)号：US08450205B2

公开(公告)日：2013-05-28

申请号：US13474244

申请日：2012-05-17

申请人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

摘要翻译： 提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。 一种结构包括层间电线之间的交叉处的通孔簇结构。 通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。 至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。

公开(公告)号：US20130106455A1

公开(公告)日：2013-05-02

申请号：US13285048

申请日：2011-10-31

申请人： Robert D. Edwards ,  Oleg Gluschenkov ,  Louis V. Medina ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

发明人： Robert D. Edwards ,  Oleg Gluschenkov ,  Louis V. Medina ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

IPC分类号： G01R31/20

CPC分类号： G01R31/2891 ,  G01R1/06794 ,  G01R1/07364

摘要： A wafer probing system includes a probe card assembly having a plurality of individual probe structures configured make contact with a semiconductor wafer mounted on a motor driven wafer chuck, with each probe structure configured with a pressure sensing unit integrated therewith; and a controller configured to drive the probe card assembly with one or more piezoelectric driver units response to feedback from the pressure sensing units of the individual probe structures.

公开(公告)号：US08378447B2

公开(公告)日：2013-02-19

申请号：US13085632

申请日：2011-04-13

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。

公开(公告)号：US08304863B2

公开(公告)日：2012-11-06

申请号：US12702463

申请日：2010-02-09

申请人： Ronald G. Filippi ,  John A. Fitzsimmons ,  Kevin Kolvenbach ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  John A. Fitzsimmons ,  Kevin Kolvenbach ,  Ping-Chuan Wang

IPC分类号： H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

摘要翻译： 贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。 每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力 。 因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。