公开(公告)号：US20070250682A1

公开(公告)日：2007-10-25

申请号：US11731747

申请日：2007-03-30

申请人： Charles Moore ,  John Rible ,  Jeffrey Fox

发明人： Charles Moore ,  John Rible ,  Jeffrey Fox

IPC分类号： G06F15/00

CPC分类号： G06F15/8023 ,  G06F9/5066 ,  G06F9/547

摘要： A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 24 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output. Mechanisms are described for communications between computers (12) and the outside environment.

摘要翻译： 计算机阵列（10）具有用于完成更大任务的多个计算机（12），其被划分成较小的任务，每个较小的任务分配给一个或多个计算机（12）。 每个计算机（12）可以被配置为用于特定功能，并且与外部计算机（12）相关联的各个输入/输出电路（26）特别适用于特定的输入/输出功能。 布置在计算机阵列（10）中的24台计算机（12）的示例具有集中式计算核心（34），其中靠近管芯（14）边缘的计算机（12）被配置为用于输入和/或输出。 描述了用于计算机（12）和外部环境之间的通信的机制。

公开(公告)号：US20070226457A1

公开(公告)日：2007-09-27

申请号：US11653187

申请日：2007-01-12

申请人： Charles Moore ,  Jeffrey Fox ,  John Rible

发明人： Charles Moore ,  Jeffrey Fox ,  John Rible

IPC分类号： G06F15/00

CPC分类号： G06F1/32

摘要： A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

摘要翻译： 一种微处理器系统，其中处理器阵列通过使用工作模式功能更有效地进行通信。 当前不执行代码的处理器保持处于非活动状态，但是在相邻处理器发送任务之前，该状态保持不活动状态。 处理器也可以编程为暂时挂起任务以检查传入的任务或消息。

公开(公告)号：US20070192566A1

公开(公告)日：2007-08-16

申请号：US11441818

申请日：2006-05-26

申请人： Charles Moore ,  Jeffrey Fox ,  John Rible

发明人： Charles Moore ,  Jeffrey Fox ,  John Rible

IPC分类号： G06F15/00

CPC分类号： G06F1/324 ,  G06F1/3209 ,  Y02D10/126

摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.

摘要翻译： 计算机阵列（10）具有多个计算机（12）。 计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。 当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入睡眠状态，直到另一台计算机（12）准备完成交易，从而节省电力并减少热量产生。 休眠计算机（12）可以等待数据或指令（12）。 在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。 在后一种情况下，当它们被接收和执行时，这些指令被放置在指令寄存器（30a）中，而不首先将指令首先置于存储器中。 指令可以包括能够重复执行一系列操作的微循环（100）。 在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

公开(公告)号：US20070192575A1

公开(公告)日：2007-08-16

申请号：US11441812

申请日：2006-05-26

申请人： Charles Moore ,  Jeffrey Fox ,  John Rible

发明人： Charles Moore ,  Jeffrey Fox ,  John Rible

IPC分类号： G06F9/44

CPC分类号： G06F9/30134 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/32 ,  G06F9/325 ,  G06F9/3885 ,  G06F9/4486 ,  G06F15/8023

摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.

摘要翻译： 计算机阵列（10）具有多个计算机（12）。 计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。 当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入睡眠状态，直到另一台计算机（12）准备完成交易，从而节省电力并减少热量产生。 休眠计算机（12）可以等待数据或指令（12）。 在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。 在后一种情况下，当它们被接收和执行时，这些指令被放置在指令寄存器（30a）中，而不首先将指令首先置于存储器中。 指令可以包括能够重复执行一系列操作的微循环（100）。 在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

公开(公告)号：US20130159376A1

公开(公告)日：2013-06-20

申请号：US13715835

申请日：2012-12-14

申请人： Charles Moore

发明人： Charles Moore

IPC分类号： H04L29/08

CPC分类号： H04L67/10 ,  G06F9/5072 ,  H04L67/2809

摘要： A resource broker agent may be configured to monitor computing resources available on a computing device. The resource broker agent may be further configured to request additional computing resources in response to detecting a request to perform a computing task that cannot be adequately performed with the computing resources currently available on the computing device. The additional computing resources may be requested from one or more remote resource providers via a network. The additional computing resources may comprise remote execution of portions of the computing task. The resource broker agent may be further configured to perform the requested computing task by use of a virtualized computing environment of the computing device.

摘要翻译： 资源代理代理可以被配置为监视计算设备上可用的计算资源。 可以进一步配置资源代理代理以响应于检测到执行计算任务的请求而无法用计算设备上当前可用的计算资源进行适当的执行来请求额外的计算资源。 可以经由网络从一个或多个远程资源提供者请求附加的计算资源。 附加的计算资源可以包括计算任务的部分的远程执行。 资源代理代理可以被进一步配置成通过使用计算设备的虚拟化计算环境来执行所请求的计算任务。

公开(公告)号：US08097709B2

公开(公告)日：2012-01-17

申请号：US12196714

申请日：2008-08-22

申请人： Aaron Peoples ,  Qibo Zhang ,  Charles Moore ,  Lucy Ling ,  Mithra Rothfeder ,  Kim Lewis

发明人： Aaron Peoples ,  Qibo Zhang ,  Charles Moore ,  Lucy Ling ,  Mithra Rothfeder ,  Kim Lewis

IPC分类号： C07H17/02 ,  A01N43/04 ,  A61K31/70

CPC分类号： C07D309/14

摘要： The invention relates generally to novel macrolactams and their analogs, to processes for the preparation of these novel macrolactams, to pharmaceutical compositions comprising the novel macrolactams; and to methods of using the novel macrolactams to treat or inhibit various disorders.

摘要翻译： 本发明一般涉及新颖的大环内酰胺及其类似物，用于制备这些新型的大内酰胺的方法，用于包含新型大环内酯的药物组合物; 以及使用新型大环内酰胺来治疗或抑制各种疾病的方法。

公开(公告)号：US20090147091A1

公开(公告)日：2009-06-11

申请号：US11987869

申请日：2007-12-05

申请人： Charles Myers ,  Michael J. Brosnan ,  Charles Moore ,  Richard A. Baumgartner ,  Christopher Silsby ,  Brian J. Misek

发明人： Charles Myers ,  Michael J. Brosnan ,  Charles Moore ,  Richard A. Baumgartner ,  Christopher Silsby ,  Brian J. Misek

IPC分类号： H04N5/228

CPC分类号： H04N5/23248 ,  H04N5/23254 ,  H04N5/2327

摘要： An imaging pixel array and associated method and system are disclosed in which the array contains first pixels each having a first photo-conversion device, and second pixels each having a first photo-conversion device and a second photo-conversion device. The first photo-conversion devices are configured to acquire an image during a first integration period. The second photo-conversion devices are configured to acquire a plurality of images during the first integration period. A circuit uses the plurality of image signals and determines from them relative motion between the array and an image during a portion of the first integration period and provides a signal representing the motion which is used for image stabilization.

摘要翻译： 公开了一种成像像素阵列及其相关联的方法和系统，其中阵列包含每个具有第一光转换装置的第一像素，以及每个具有第一光转换装置和第二光转换装置的第二像素。 第一光转换装置被配置为在第一积分周期期间获取图像。 第二光转换装置被配置为在第一积分周期期间获取多个图像。 电路使用多个图像信号，并且在第一积分周期的一部分期间从其确定阵列与图像之间的相对运动，并且提供表示用于图像稳定的运动的信号。

公开(公告)号：US20060208805A1

公开(公告)日：2006-09-21

申请号：US11084376

申请日：2005-03-18

申请人： Brian Galloway ,  Gunter Steinbach ,  Charles Moore

发明人： Brian Galloway ,  Gunter Steinbach ,  Charles Moore

IPC分类号： H03L7/00

CPC分类号： H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/06

摘要： A linear PLL includes a VCO with first and second tuning elements. The first tuning element is adjusted in proportion to the phase error between an input signal and a VCO signal and the second tuning element is adjusted by an integral function of the phase error. By configuring the VCO with separate tuning elements that are separately adjusted in proportion to the phase error and by an integral function of the phase error, the 3 dB bandwidth frequency of the linear PLL depends primarily on the phase detector gain and the VCO gain that is contributed from the proportional adjustment. A linear PLL with separate proportional and integral tuning elements can be designed to exhibit a relatively constant gain over a relatively large frequency range.

摘要翻译： 线性PLL包括具有第一和第二调谐元件的VCO。 第一调谐元件与输入信号和VCO信号之间的相位误差成比例地调整，并且通过相位误差的积分函数来调整第二调谐元件。 通过使用单独的调谐元件配置VCO，该调谐元件与相位误差成比例地分别调整，并通过相位误差的积分函数，线性PLL的3 dB带宽频率主要取决于相位检测器增益和VCO增益 由比例调整贡献。 具有分开的比例和积分调谐元件的线性PLL可以设计成在相对大的频率范围内呈现相对恒定的增益。

公开(公告)号：US20050121766A1

公开(公告)日：2005-06-09

申请号：US11031774

申请日：2005-01-07

申请人： Nurwati Devnani ,  James Barnes ,  Charles Moore ,  Benny Lai

发明人： Nurwati Devnani ,  James Barnes ,  Charles Moore ,  Benny Lai

IPC分类号： H01L21/44 ,  H01L23/498 ,  H01L23/52 ,  H01L23/64

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011

摘要： A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

摘要翻译： 封装的IC包括具有相对于彼此定位的信号和信号补偿迹线的IC管芯，以使匹配阻抗最大化边缘耦合。 信号和信号补码迹线电连接到IC芯片的传输或接收通道。 使用宽边耦合迹线配置减轻了IC封装中的布线拥塞，并允许IC在给定的表面区域内容纳比现有技术中可能的更多数量的通道。

公开(公告)号：US5999028A

公开(公告)日：1999-12-07

申请号：US995886

申请日：1997-12-22

申请人： Ulrich Knoch ,  Thorsten Krueger ,  Barbara Duffner ,  Ronnie Owens ,  Charles Moore

发明人： Ulrich Knoch ,  Thorsten Krueger ,  Barbara Duffner ,  Ronnie Owens ,  Charles Moore

IPC分类号： H03K19/0944 ,  H03F3/45 ,  H03K5/24 ,  H03K5/12 ,  G06G7/10

CPC分类号： H03F3/45771 ,  H03F3/45479 ,  H03K5/2481 ,  H03F2203/45624 ,  H03F2203/45646 ,  H03F2203/45702

摘要： Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.

摘要翻译： 描述了一种用于在两个基本上对称构建的电流路径处接收差分输入信号并用于从其提供输出信号的电路。 至少一个电流路径包括用于将输入信号的定时信息调整为输出信号的定时信息的装置。 可以通过修改相应电流路径中的电压电平来实现调整，直到输出信号的定时信息至少基本上表示输入信号的定时信息，例如， 通过修改各个电流路径中的阻抗或电流。 通过用已知的定时信息应用定义的输入信号来执行定时信息的调整，将所得到的输出信号的定时信息与输入信号的定时信息进行比较，并修改至少一个电压电平 直到输出和输入信号的定时信息至少基本匹配的电流路径。