公开(公告)号：US06421053B1

公开(公告)日：2002-07-16

申请号：US09316097

申请日：1999-05-24

申请人： Charles Ray Johns ,  John Samuel Liberty ,  Brad William Michael ,  John Fred Spannaus

发明人： Charles Ray Johns ,  John Samuel Liberty ,  Brad William Michael ,  John Fred Spannaus

IPC分类号： G06T1120

CPC分类号： G06T15/80

摘要： Primitives are divided into span groups of 2N spans, and then processed in M×N blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group. Once the first end of a span group is reached, the values for the initial or entry block are popped from the stack and rendering resumes from the initial or entry block in the opposite direction, but in the same serpentine or zig-zag manner, until the other end of the span group is reached. The next span group, if any, is rendered starting with a block adjacent to the last block rendered in the previous span group. Memory bandwidth utilization between the pixel and texel cache and the frame buffer is thus improved, together with texel reuse during texture mapping, to reduce the total number of pixel and texel fetches required to render the primitive.

摘要翻译： 原子被分成2N个跨度的跨度组，然后在M×N个像素块中进行处理，其中像素块优选尽可能接近正方形，因此针对小跨度和纹理映射进行优化。 每个跨度组以蛇形方式从初始或进入块逐块渲染，首先在远离原始长边的方向上，然后朝向长边的方向。 插值器包括一个深层堆叠，在渲染跨度组内的任何其他块之前，将初始或进入块的像素和纹素信息推送到其上。 然后交替地渲染跨度组的不同跨度子组内的块或块对，使得当它进行到跨度组的末尾时，在跨越子组之间渲染之字形。 一旦达到跨度组的第一个结束，初始或进入块的值从堆栈中弹出，并且渲染从初始或进入块以相反方向恢复，但是以相同的蛇形或锯齿形方式恢复，直到 到达跨度组的另一端。 下一个范围组（如果有的话）从与前一个范围组中呈现的最后一个块相邻的块开始绘制。 因此，像素和纹素高速缓存和帧缓冲器之间的存储器带宽利用率在纹理映射期间与纹素复用一起得到改善，以减少呈现原始图像所需的像素和纹素提取的总数。

公开(公告)号：US07986330B2

公开(公告)日：2011-07-26

申请号：US09833348

申请日：2001-04-12

申请人： Daniel Alan Brokenshire ,  Bruce David D'Amora ,  Gordon Clyde Fossum ,  Charles Ray Johns ,  John Samuel Liberty ,  Brad William Michael

发明人： Daniel Alan Brokenshire ,  Bruce David D'Amora ,  Gordon Clyde Fossum ,  Charles Ray Johns ,  John Samuel Liberty ,  Brad William Michael

IPC分类号： G09G5/00

CPC分类号： G09G5/393 ,  G06T11/203 ,  G06T2200/12 ,  G09G2320/0276 ,  G09G2340/10

摘要： A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.

摘要翻译： 一种用于生成用于在数据处理系统中显示的抗锯齿线的方法，装置和计算机实现的指令。 接收用于显示的图形数据，其中图形数据包括定义线的图元。 基于每个原始图像数据应用伽马校正以形成抗锯齿线。 显示抗锯齿线。

公开(公告)号：US5790125A

公开(公告)日：1998-08-04

申请号：US636093

申请日：1996-04-22

申请人： Thuy-Linh Tran Bui ,  Charles Ray Johns ,  John Thomas Roberson ,  John Fred Spannaus

发明人： Thuy-Linh Tran Bui ,  Charles Ray Johns ,  John Thomas Roberson ,  John Fred Spannaus

IPC分类号： G06F5/00 ,  G06F3/14 ,  G06T11/00 ,  G06T15/00

CPC分类号： G06F3/14

摘要： Graphics information is efficiently transferred from a host computer to a graphics subsystem in which rendering and pixel data is generated by the host system. A masked span operation provides an assist for 3D rendering performed by the system processor of the host and other system resources. Storage of depth, alpha, stencil, and other pixel data is in system memory including one or more ancillary graphics buffers. The main processor of the host system generates pixel data associated with an image. This data is checked against the buffers. As a result of such checking, a mask is generated by the host system. The mask is transferred in burst mode across the host-graphic subsystem PCI bus to the graphics subsystem in combination with span width, and in the case of interpolated color, color base and color increment data, and X,Y coordinate of the first pixel. In the graphics subsystem the mask is employed with the other data to load the frame buffer with the portion of pixel data defined by the mask.

摘要翻译： 图形信息从主计算机有效地传送到图形子系统，其中渲染和像素数据由主机系统生成。 屏蔽跨度操作提供了由主机的系统处理器和其他系统资源执行的3D渲染的辅助。 深度，阿尔法，模板和其他像素数据的存储在系统存储器中，包括一个或多个辅助图形缓冲器。 主机系统的主处理器生成与图像相关联的像素数据。 此缓冲区检查此数据。 作为这种检查的结果，主机系统产生掩码。 掩模以突发模式通过主机图形子系统PCI总线传送到图形子系统，并结合跨度宽度，并且在内插颜色，色底和颜色增量数据以及第一像素的X，Y坐标的情况下。 在图形子系统中，使用掩码与其他数据一起加载由该掩码定义的像素数据部分的帧缓冲器。

公开(公告)号：US06760819B2

公开(公告)日：2004-07-06

申请号：US09895888

申请日：2001-06-29

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty ,  Thuong Quang Truong

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty ,  Thuong Quang Truong

IPC分类号： G06F1208

CPC分类号： G06F12/0822 ,  G06F12/0811 ,  G06F12/084

摘要： A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.

摘要翻译： 提供具有共享低级高速缓存（或存储器）的多处理器数据处理系统中的处理器 - 高速缓存操作方案和拓扑，通过该共享低级高速缓存（或存储器）减少一致性总线的数量并且提供与处理器高速缓存更有效的窥探分辨率和一致性操作。 在低级（L2）高速缓存或内存中提供内部（L1）缓存目录的副本。 通过将侦听地址与L2缓存中L1目录的副本的地址标签进行比较，完成L1目录的侦听操作和一致性维护操作。 对L1目录的副本的一致性状态的更新被镜像在L1目录和L1缓存中。 这消除了对耦合到L2高速缓存的每个处理器的各个一致性总线的需要，并且加速一致性操作，因为该探测不必被传送到L1高速缓存。

公开(公告)号：US07836222B2

公开(公告)日：2010-11-16

申请号：US10606582

申请日：2003-06-26

申请人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

发明人： Michael Norman Day ,  Brian King Flachs ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

IPC分类号： G06F3/00 ,  G11C8/00

CPC分类号： H04Q3/545 ,  H04Q2213/13106

摘要： An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.

摘要翻译： 使用信道计数器与信道计数读取指令组合的装置作为提供给定信道中的数据有效或先前未被读取的信息的手段。 在信道被定义为阻塞的情况下，计数器还可以用于防止在信道使用的寄存器中无意中覆盖数据，或者替代地，当给定计数时，防止与分配给该信道的设备的进一步通信 发生。 智能外部设备还可以使用发送到计数机构的通道计数读取指令来读取和写入通道。

公开(公告)号：US08838950B2

公开(公告)日：2014-09-16

申请号：US10601374

申请日：2003-06-23

申请人： David John Craft ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

发明人： David John Craft ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  John Samuel Liberty

IPC分类号： G06F21/00 ,  H04L9/32 ,  G06F21/53

CPC分类号： G06F21/53 ,  H04L9/3226 ,  H04L2209/56

摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.

摘要翻译： 本发明提供了验证代码和/或数据并提供受保护的环境以供执行。 本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。 本地商店被划分成一个隔离和非隔离的部分。 代码或数据被加载到隔离的部分。 代码或数据在本地存储的隔离部分进行身份验证。 认证后，执行代码。 在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。

公开(公告)号：US08483227B2

公开(公告)日：2013-07-09

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/56

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US07975064B2

公开(公告)日：2011-07-05

申请号：US10942422

申请日：2004-09-16

申请人： Michael Joseph Carnevale ,  Scott Douglas Clark ,  David Wayne Hill ,  Charles Ray Johns ,  Thomas K. Pokrandt ,  Jeffrey Joseph Ruedinger ,  Dorothy Marie Thelen

发明人： Michael Joseph Carnevale ,  Scott Douglas Clark ,  David Wayne Hill ,  Charles Ray Johns ,  Thomas K. Pokrandt ,  Jeffrey Joseph Ruedinger ,  Dorothy Marie Thelen

IPC分类号： G06F15/16

CPC分类号： H04L1/188

摘要： A mechanism provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

摘要翻译： 一种机制用于发送信封并回复信封。 发射机被配置为发送信封。 接收机耦合到发射机，其中接收机被配置为接收信封并产生回复信封。 发送缓冲器耦合到发送器。 接收缓冲器耦合到接收器。 重试定时器耦合到发射机，其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。 如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络，则发射机被配置为重发信封。 这导致从发射机和接收机两者发送的信封总数的减少。

公开(公告)号：US07802023B2

公开(公告)日：2010-09-21

申请号：US11250246

申请日：2005-10-14

申请人： Takeshi Yamazaki ,  Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

发明人： Takeshi Yamazaki ,  Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： G06F12/0815 ,  G06F12/0835

摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

摘要翻译： 方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

公开(公告)号：US07725618B2

公开(公告)日：2010-05-25

申请号：US10902474

申请日：2004-07-29

申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。