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    System and method for use in a computerized imaging system to efficiently transfer graphics information to a graphics subsystem employing masked span
    1.
    发明授权
    System and method for use in a computerized imaging system to efficiently transfer graphics information to a graphics subsystem employing masked span 失效
    用于计算机化成像系统中的系统和方法用于将图形信息有效地传送到使用掩蔽跨度的图形子系统

    公开(公告)号：US5790125A

    公开(公告)日：1998-08-04

    申请号：US636093

    申请日：1996-04-22

    申请人： Thuy-Linh Tran Bui ,  Charles Ray Johns ,  John Thomas Roberson ,  John Fred Spannaus

    发明人： Thuy-Linh Tran Bui ,  Charles Ray Johns ,  John Thomas Roberson ,  John Fred Spannaus

    IPC分类号： G06F5/00 ,  G06F3/14 ,  G06T11/00 ,  G06T15/00

    CPC分类号： G06F3/14

    摘要： Graphics information is efficiently transferred from a host computer to a graphics subsystem in which rendering and pixel data is generated by the host system. A masked span operation provides an assist for 3D rendering performed by the system processor of the host and other system resources. Storage of depth, alpha, stencil, and other pixel data is in system memory including one or more ancillary graphics buffers. The main processor of the host system generates pixel data associated with an image. This data is checked against the buffers. As a result of such checking, a mask is generated by the host system. The mask is transferred in burst mode across the host-graphic subsystem PCI bus to the graphics subsystem in combination with span width, and in the case of interpolated color, color base and color increment data, and X,Y coordinate of the first pixel. In the graphics subsystem the mask is employed with the other data to load the frame buffer with the portion of pixel data defined by the mask.

    摘要翻译： 图形信息从主计算机有效地传送到图形子系统，其中渲染和像素数据由主机系统生成。 屏蔽跨度操作提供了由主机的系统处理器和其他系统资源执行的3D渲染的辅助。 深度，阿尔法，模板和其他像素数据的存储在系统存储器中，包括一个或多个辅助图形缓冲器。 主机系统的主处理器生成与图像相关联的像素数据。 此缓冲区检查此数据。 作为这种检查的结果，主机系统产生掩码。 掩模以突发模式通过主机图形子系统PCI总线传送到图形子系统，并结合跨度宽度，并且在内插颜色，色底和颜色增量数据以及第一像素的X，Y坐标的情况下。 在图形子系统中，使用掩码与其他数据一起加载由该掩码定义的像素数据部分的帧缓冲器。

    Block rendering method for a graphics subsystem
    2.
    发明授权
    Block rendering method for a graphics subsystem 有权
    图形子系统的块渲染方法

    公开(公告)号：US06421053B1

    公开(公告)日：2002-07-16

    申请号：US09316097

    申请日：1999-05-24

    申请人： Charles Ray Johns ,  John Samuel Liberty ,  Brad William Michael ,  John Fred Spannaus

    发明人： Charles Ray Johns ,  John Samuel Liberty ,  Brad William Michael ,  John Fred Spannaus

    IPC分类号： G06T1120

    CPC分类号： G06T15/80

    摘要： Primitives are divided into span groups of 2N spans, and then processed in M×N blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group. Once the first end of a span group is reached, the values for the initial or entry block are popped from the stack and rendering resumes from the initial or entry block in the opposite direction, but in the same serpentine or zig-zag manner, until the other end of the span group is reached. The next span group, if any, is rendered starting with a block adjacent to the last block rendered in the previous span group. Memory bandwidth utilization between the pixel and texel cache and the frame buffer is thus improved, together with texel reuse during texture mapping, to reduce the total number of pixel and texel fetches required to render the primitive.

    摘要翻译： 原子被分成2N个跨度的跨度组，然后在M×N个像素块中进行处理，其中像素块优选尽可能接近正方形，因此针对小跨度和纹理映射进行优化。 每个跨度组以蛇形方式从初始或进入块逐块渲染，首先在远离原始长边的方向上，然后朝向长边的方向。 插值器包括一个深层堆叠，在渲染跨度组内的任何其他块之前，将初始或进入块的像素和纹素信息推送到其上。 然后交替地渲染跨度组的不同跨度子组内的块或块对，使得当它进行到跨度组的末尾时，在跨越子组之间渲染之字形。 一旦达到跨度组的第一个结束，初始或进入块的值从堆栈中弹出，并且渲染从初始或进入块以相反方向恢复，但是以相同的蛇形或锯齿形方式恢复，直到 到达跨度组的另一端。 下一个范围组（如果有的话）从与前一个范围组中呈现的最后一个块相邻的块开始绘制。 因此，像素和纹素高速缓存和帧缓冲器之间的存储器带宽利用率在纹理映射期间与纹素复用一起得到改善，以减少呈现原始图像所需的像素和纹素提取的总数。

    Display graphics adapter for processing different pixel sizes in a windowing system
    3.
    发明授权
    Display graphics adapter for processing different pixel sizes in a windowing system 失效
    显示图形适配器，用于在窗口系统中处理不同像素大小

    公开(公告)号：US5724560A

    公开(公告)日：1998-03-03

    申请号：US572697

    申请日：1995-12-14

    申请人： Charles Ray Johns ,  John Thomas Roberson

    发明人： Charles Ray Johns ,  John Thomas Roberson

    IPC分类号： G06F12/02 ,  G06F3/153 ,  G06T1/20 ,  G06T1/60 ,  G09G5/00 ,  G09G5/02 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/397 ,  G09G5/399

    CPC分类号： G06T1/60 ,  G09G5/393 ,  G09G5/395 ,  G09G2360/12

    摘要： A graphics adapter having a processor for processing pixel data is provided. The processor transfers the processed data to the graphics memory in sets of slices of pixel data where each transfer provides several slices, each slice being from a unique pixel. In an alternative embodiment, the storage of the processed data is accomplished within a plurality of memory banks, each of the memory banks being used to store slices of consecutive pixels. The invention further provides for concurrently displaying images having different color depths. This is achieved by a method of organizing data of different pixel depths such that they can be interpreted correctly. Furthermore, the invention provides for double buffering the processed data to get a smooth transition from one image to another.

    摘要翻译： 提供了具有用于处理像素数据的处理器的图形适配器。 处理器将处理的数据以像素数据片段的集合传送到图形存储器，其中每个传输提供多个片段，每个片段来自唯一的像素。 在替代实施例中，处理的数据的存储在多个存储体中完成，每个存储器组用于存储连续像素的片段。 本发明还提供同时显示具有不同颜色深度的图像。 这通过组织不同像素深度的数据的方法来实现，使得它们可以被正确解释。 此外，本发明提供了对缓冲处理数据进行双重缓冲以获得从一个图像到另一个图像的平滑过渡。

    Controlling bandwidth reservations method and apparatus
    5.
    发明授权
    Controlling bandwidth reservations method and apparatus 有权
    控制带宽预留方法和装置

    公开(公告)号：US08483227B2

    公开(公告)日：2013-07-09

    申请号：US10718302

    申请日：2003-11-20

    申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

    发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

    IPC分类号： H04L12/56

    CPC分类号： H04L41/0896

    摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

    摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

    Envelope packet architecture for broadband engine
    6.
    发明授权
    Envelope packet architecture for broadband engine 有权
    宽带引擎的信封包架构

    公开(公告)号：US07975064B2

    公开(公告)日：2011-07-05

    申请号：US10942422

    申请日：2004-09-16

    申请人： Michael Joseph Carnevale ,  Scott Douglas Clark ,  David Wayne Hill ,  Charles Ray Johns ,  Thomas K. Pokrandt ,  Jeffrey Joseph Ruedinger ,  Dorothy Marie Thelen

    发明人： Michael Joseph Carnevale ,  Scott Douglas Clark ,  David Wayne Hill ,  Charles Ray Johns ,  Thomas K. Pokrandt ,  Jeffrey Joseph Ruedinger ,  Dorothy Marie Thelen

    IPC分类号： G06F15/16

    CPC分类号： H04L1/188

    摘要： A mechanism provides for sending an envelope and replying to an envelope. A transmitter is configured to send an envelope. A receiver is coupled to the transmitter, wherein the receiver is configured to receive the envelope and generate a reply envelope. A send buffer is coupled to the transmitter. A receive buffer is coupled to the receiver. A retry timer is coupled to the transmitter, wherein the retry timer is configured to reset upon the receipt of a reply envelope correlated to the transmit envelope. The transmitter is configured to retransmit an envelope if the transmitter does not receive a corresponding reply envelope within a selected time period as determined by the retry timer. This leads to a decrease in the total number of envelopes, transmitted from both the transmitter and the receiver.

    摘要翻译： 一种机制用于发送信封并回复信封。 发射机被配置为发送信封。 接收机耦合到发射机，其中接收机被配置为接收信封并产生回复信封。 发送缓冲器耦合到发送器。 接收缓冲器耦合到接收器。 重试定时器耦合到发射机，其中重试定时器被配置为在接收到与发射包络相关的应答包络时复位。 如果发射机在由重试定时器确定的选定时间段内没有接收到对应的应答包络，则发射机被配置为重发信封。 这导致从发射机和接收机两者发送的信封总数的减少。

    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment
    8.
    发明授权
    Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
    非对称异构多处理器环境中的内存障碍原语

    公开(公告)号：US07725618B2

    公开(公告)日：2010-05-25

    申请号：US10902474

    申请日：2004-07-29

    申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

    摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

    Directory for multi-node coherent bus
    10.
    发明授权
    Directory for multi-node coherent bus 有权
    多节点相干总线目录

    公开(公告)号：US07669013B2

    公开(公告)日：2010-02-23

    申请号：US11828439

    申请日：2007-07-26

    申请人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

    发明人： Gary Dale Carpenter ,  Scott Douglas Clark ,  Bernard Charles Drerup ,  Russell Dean Hoover ,  Charles Ray Johns ,  David John Krolak ,  Prasanna Srinivasan ,  Thuong Quang Truong

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0817 ,  G06F12/0831

    摘要： A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.

    摘要翻译： 一种使用允许较少前进进度依赖性的专用桥来维护多节点系统的高速缓存一致性的方法。 如果在本地节点的多节点桥接处接收到的请求是系统请求，则执行本地节点目录的查找。 如果目录项指示请求中指定的数据具有本地所有者或本地目标，则请求将转发到本地节点。 如果本地节点确定请求是本地请求，则执行本地节点目录的查找。 如果目录条目指示请求中指定的数据具有本地所有者和本地目标，则解析本地节点上的数据的一致性，并且如果需要，则执行请求数据的传输。 否则，请求将转发到多节点系统中的所有远程节点。