Side by side light emitting diode (LED) having separate electrical and heat transfer paths
    1.
    发明授权
    Side by side light emitting diode (LED) having separate electrical and heat transfer paths 有权
    具有独立的电和热传递路径的并排发光二极管(LED)

    公开(公告)号:US08552458B2

    公开(公告)日:2013-10-08

    申请号:US12824163

    申请日:2010-06-26

    IPC分类号: H01L33/02

    摘要: A light emitting diode includes a thermal conductive substrate having at least one electrical isolation layer configured to provide vertical electrical isolation and a heat transfer path through the substrate from a front side (first side) to a back side (second side) thereof. The light emitting diode includes an anode having a through interconnect, and a cathode having a through interconnect, which are arranged side by side on the substrate. The light emitting diode also includes a LED chip mounted to the substrate between the anode and the cathode. A method for fabricating the light emitting diode includes the steps of providing a thermal conductive substrate having an electrical isolation layer, forming an anode via and a cathode via side by side on a first side of the substrate part way through the substrate, forming an anode through interconnect in the anode via and a cathode through interconnect in the cathode via, thinning the substrate from a second side of the substrate to the anode through interconnect and the cathode through interconnect, and mounting a LED chip to the first side in electrical communication with the cathode through interconnect and the anode through interconnect.

    摘要翻译: 发光二极管包括具有至少一个电隔离层的导热基板,该隔离层被配置为提供垂直电隔离和从基板的前侧(第一侧)到其后侧(第二侧)穿过基板的热传递路径。 发光二极管包括具有贯通互连的阳极和在基板上并排布置的具有通孔互连的阴极。 发光二极管还包括安装在阳极和阴极之间的衬底上的LED芯片。 一种制造发光二极管的方法包括以下步骤:提供具有电隔离层的导热衬底,在衬底的第一侧经由衬底并排形成阳极通孔和阴极,形成阳极 通过在阴极通孔中通过互连在阳极通孔和阴极之间的互连,通过互连将互连和阴极通过互连将衬底从衬底的第二侧延伸到阳极,并将LED芯片安装到与第一侧电连通的第一侧 阴极通过互连和阳极通过互连。

    PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES
    3.
    发明申请
    PROTECTION FOR THE EPITAXIAL STRUCTURE OF METAL DEVICES 审中-公开
    金属器件外延结构的保护

    公开(公告)号:US20120074384A1

    公开(公告)日:2012-03-29

    申请号:US13310552

    申请日:2011-12-02

    IPC分类号: H01L33/06

    摘要: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non-(or low) thermally conductive and/or non-(or low) electrically conductive carrier substrate that has been removed.

    摘要翻译: 提供了用于制造金属器件的技术,例如垂直发光二极管(VLED)器件,功率器件,激光二极管和垂直腔表面发射激光器件。 相应地生产的器件可以比常规金属器件更高的产量和更高的性能受益,例如发光二极管的较高的亮度和增加的导热性。 此外,本发明公开了在具有原始非导热和/或非导电性的金属器件的高散热率的情况下适用于GaN基电子器件的制造技术中的技术。 (或低)导电载体衬底。

    VERTICAL LIGHT EMITTING DIODE HAVING AN OUTWARDLY DISPOSED ELECTRODE
    4.
    发明申请
    VERTICAL LIGHT EMITTING DIODE HAVING AN OUTWARDLY DISPOSED ELECTRODE 有权
    具有外部电极的垂直发光二极管

    公开(公告)号:US20110108851A1

    公开(公告)日:2011-05-12

    申请号:US12939984

    申请日:2010-11-04

    IPC分类号: H01L33/32 H01L33/62

    摘要: The invention relates to a vertical light emitting diode (VLED) having an outwardly disposed electrode, the vertical light emitting diode comprises a conductive base, a semiconductor epitaxial structure formed on the conductive base, a passivation layer formed at the periphery of the semiconductor epitaxial structure, and a conductive frame formed on the passivation layer and contacting with the edge of the upper surface of the semiconductor epitaxial structure such that the conductive frame is electrically connected to the semiconductor epitaxial structure.

    摘要翻译: 本发明涉及一种具有向外设置的电极的垂直发光二极管(VLED),垂直发光二极管包括导电基底,形成在导电基底上的半导体外延结构,形成在半导体外延结构周边的钝化层 以及形成在钝化层上并与半导体外延结构的上表面的边缘接触的导电框架,使得导电框架电连接到半导体外延结构。