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    Method of forming a protective layer included in metal filled semiconductor features
    1.
    发明授权
    Method of forming a protective layer included in metal filled semiconductor features 有权
    包含在金属填充的半导体特征中的保护层的形成方法

    公开(公告)号：US06555474B1

    公开(公告)日：2003-04-29

    申请号：US10060820

    申请日：2002-01-29

    申请人： Cheng Lin Huang ,  Minghsing Tsai ,  Winston Shue ,  Mong-Song Liang

    发明人： Cheng Lin Huang ,  Minghsing Tsai ,  Winston Shue ,  Mong-Song Liang

    IPC分类号： H01L2144

    CPC分类号： H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76873

    摘要： A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.

    摘要翻译： 一种形成包含在金属填充的半导体特征中的保护层的方法，包括提供包括具有用于形成半导体特征的各向异性蚀刻开口的绝缘介电材料的基板; 在所述半导体特征上共形沉积至少一个金属层以基本上填充所述至少一部分所述至少一个含有掺杂杂质的金属层的所述半导体特征; 并且将衬底热处理足以重新分布掺杂剂杂质的时间段，以优先地沿着至少一个金属层的周边收集。

    Method for integrating an electrodeposition and electro-mechanical polishing process
    5.
    发明授权
    Method for integrating an electrodeposition and electro-mechanical polishing process 失效
    整合电沉积和机电抛光工艺的方法

    公开(公告)号：US06793797B2

    公开(公告)日：2004-09-21

    申请号：US10106733

    申请日：2002-03-26

    申请人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Winston Shue ,  Mong-Song Liang

    发明人： Shih-Wei Chou ,  Ming-Hsing Tsai ,  Winston Shue ,  Mong-Song Liang

    IPC分类号： C25D518

    CPC分类号： H01L21/2885 ,  B23H5/08 ,  C25D5/18 ,  C25D7/123 ,  H01L21/32125 ,  H01L21/76877

    摘要： A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.

    摘要翻译： 一种用于交替电沉积和电机械抛光以选择性地用金属填充半导体特征的方法，包括：a）提供以间隔开的关系设置的阳极组件和半导体晶片，所述阳极组件和半导体晶片在半导体晶片之间包括电解质，所述电解质包括包括各向异性蚀刻特征 安排电沉积过程; b）在阳极组件和半导体晶片之间施加电位以在第一电流密度下引起电解质流动，以将金属填充部分电沉积到工艺表面上; c）逆转电位以在第二电流密度下反转电解质流动，以在电抛光过程中电镀处理表面; 以及d）依次重复步骤b和c以电沉积至少第二金属填充部分以基本上填充各向异性蚀刻的特征。

    Copper back-end-of-line by electropolish
    6.
    发明授权
    Copper back-end-of-line by electropolish 有权
    铜后线通过电解抛光

    公开(公告)号：US06649513B1

    公开(公告)日：2003-11-18

    申请号：US10146286

    申请日：2002-05-15

    申请人： Ming-Hsing Tsai ,  Shih-Wei Chou ,  Winston Shue ,  Mong-Song Liang

    发明人： Ming-Hsing Tsai ,  Shih-Wei Chou ,  Winston Shue ,  Mong-Song Liang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76831 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877

    摘要： A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.

    摘要翻译： 一种制造平面化金属结构的方法，包括以下步骤。 提供了一种结构。 在该结构上形成图案化的介电层。 所述图案化介电层具有形成在其中的开口并暴露所述结构的至少一部分。 在填充开口的图案化电介质层上形成第一金属层。 第一金属层至少包括邻近图案化介电层的掺杂金属部分。 掺杂金属部分掺杂有第二金属。 将该结构退火以形成邻近图案化介电层的第二金属氧化物层。 第一金属层和第二金属氧化物层仅使用电解抛光工艺进行平面化，以从图案化的介电层上除去过量的第一金属层和第二金属氧化物层，并在其内部留下平坦化的金属结构 开放

    Composite barrier layer
    7.
    发明授权
    Composite barrier layer 有权
    复合阻挡层

    公开(公告)号：US07453149B2

    公开(公告)日：2008-11-18

    申请号：US11024916

    申请日：2004-12-28

    申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

    摘要： A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

    摘要翻译： 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

    Composite barrier layer
    8.
    发明申请
    Composite barrier layer 有权
    复合阻挡层

    公开(公告)号：US20060027925A1

    公开(公告)日：2006-02-09

    申请号：US11024916

    申请日：2004-12-28

    申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    IPC分类号： H01L29/788

    CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

    摘要： A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

    摘要翻译： 当复合阻挡层延伸穿过整个半导体器件时，复合阻挡层为介电材料和导电材料提供优异的阻挡质量和优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常设置成与电介质材料形成边界，并且通常设置结晶层以与诸如互连材料的导电材料形成边界。

    Method for forming composite barrier layer
    9.
    发明授权
    Method for forming composite barrier layer 有权
    形成复合阻挡层的方法

    公开(公告)号：US08034709B2

    公开(公告)日：2011-10-11

    申请号：US12287516

    申请日：2008-10-10

    申请人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    发明人： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

    摘要： Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

    摘要翻译： 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种介电材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。