公开(公告)号：US07830163B2

公开(公告)日：2010-11-09

申请号：US12247040

申请日：2008-10-07

申请人： Cheng-Yung Teng ,  Li-Jieu Hsu ,  Wei-Fen Chiang ,  Yung-Yu Wu ,  Hung-Wei Chen ,  Huei-Huang Chen

发明人： Cheng-Yung Teng ,  Li-Jieu Hsu ,  Wei-Fen Chiang ,  Yung-Yu Wu ,  Hung-Wei Chen ,  Huei-Huang Chen

IPC分类号： G01R31/02

CPC分类号： G01R31/2889

摘要： The invention discloses a testing circuit board for placing a device under test and further testing the device under test according to a plurality of testing signals generated by a tester. The testing circuit board includes a circuit board and a plurality of sets of sockets. The circuit board includes a plurality of connecting holes. The plurality of sets of sockets are located on a plurality of connecting holes and electrically connects to the device under test via a plurality of connecting interfaces for transferring the plurality of testing signals to test the device under test.

摘要翻译： 本发明公开了一种用于放置被测器件的测试电路板，并根据由测试仪产生的多个测试信号进一步测试被测器件。 测试电路板包括电路板和多套插座。 电路板包括多个连接孔。 多组插座位于多个连接孔上，并通过多个连接接口与被测设备电连接，用于传送多个测试信号以测试待测设备。

公开(公告)号：US20070268037A1

公开(公告)日：2007-11-22

申请号：US11608226

申请日：2006-12-07

申请人： Cheng-Yung Teng ,  Yi-Chang Hsu ,  Wei-Fen Chiang ,  Hung-Wei Chen

发明人： Cheng-Yung Teng ,  Yi-Chang Hsu ,  Wei-Fen Chiang ,  Hung-Wei Chen

IPC分类号： G01R31/26

CPC分类号： G01R31/3167

摘要： The present invention discloses a circuit testing apparatus for testing a device under test. The circuit testing apparatus includes a signal transformation module, a meter, and a logic tester. The signal transformation module is coupled to the device under test and transforms an analog output signal generated by the device under test into a DC signal. The meter is coupled to the signal transformation module and measures the DC signal so as to generate a digital measuring result. The logic tester is coupled to the meter and determines a test result for the device under test according to the digital measuring result.

摘要翻译： 本发明公开了一种用于测试被测器件的电路测试装置。 电路测试装置包括信号变换模块，仪表和逻辑测试仪。 信号变换模块耦合到被测器件，并将由被测器件产生的模拟输出信号转换为直流信号。 仪表耦合到信号变换模块，测量直流信号，产生数字测量结果。 逻辑测试仪与仪表相连，根据数字测量结果确定被测设备的测试结果。

公开(公告)号：US20080191730A1

公开(公告)日：2008-08-14

申请号：US11798000

申请日：2007-05-09

申请人： Cheng-Yung Teng ,  Hung-Wei Chen ,  Yung-Yu Wu

发明人： Cheng-Yung Teng ,  Hung-Wei Chen ,  Yung-Yu Wu

IPC分类号： G01R31/26

CPC分类号： G01R31/31935

摘要： The invention discloses a circuit testing apparatus for testing a device under testing. The circuit testing apparatus includes a logic tester and a signal-measuring module. The logic tester is coupled to the device under testing for providing a testing signal and a trigger signal, and then determining a testing result for the device under testing according to a digital measuring result. The signal-measuring module coupled to the device under testing and the logic tester, is utilized for measuring a DC signal generated by the device under testing according to the testing signal after receiving the trigger signal, and generating the digital measuring result.

摘要翻译： 本发明公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括逻辑测试仪和信号测量模块。 逻辑测试器耦合到被测器件，以提供测试信号和触发信号，然后根据数字测量结果确定被测器件的测试结果。 耦合到待测器件的信号测量模块和逻辑测试器，用于在接收到触发信号之后根据测试信号测量被测器件产生的直流信号，并产生数字测量结果。

公开(公告)号：US08148996B2

公开(公告)日：2012-04-03

申请号：US11798000

申请日：2007-05-09

申请人： Cheng-Yung Teng ,  Hung-Wei Chen ,  Yung-Yu Wu

发明人： Cheng-Yung Teng ,  Hung-Wei Chen ,  Yung-Yu Wu

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/31935

摘要： The invention discloses a circuit testing apparatus for testing a device under testing. The circuit testing apparatus includes a logic tester and a signal-measuring module. The logic tester is coupled to the device under testing for providing a testing signal and a trigger signal, and then determining a testing result for the device under testing according to a digital measuring result. The signal-measuring module coupled to the device under testing and the logic tester, is utilized for measuring a DC signal generated by the device under testing according to the testing signal after receiving the trigger signal, and generating the digital measuring result.

摘要翻译： 本发明公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括逻辑测试器和信号测量模块。 逻辑测试器耦合到被测器件，以提供测试信号和触发信号，然后根据数字测量结果确定被测器件的测试结果。 耦合到待测器件的信号测量模块和逻辑测试器，用于在接收到触发信号之后根据测试信号测量被测器件产生的直流信号，并产生数字测量结果。

公开(公告)号：US07642801B2

公开(公告)日：2010-01-05

申请号：US11898317

申请日：2007-09-11

申请人： Cheng-Yung Teng ,  Hung-Wei Chen

发明人： Cheng-Yung Teng ,  Hung-Wei Chen

IPC分类号： G01R31/26

CPC分类号： G01R31/31932 ,  G01R31/31924

摘要： A circuit testing apparatus for testing a device under test is disclosed. The circuit testing apparatus includes a function generator, a signal measuring module and a determining module. The function generator is coupled to the device under test for providing a plurality of testing signals according to a predetermined manner. The signal measuring module is coupled to the device under test and the function module for measuring a plurality of measuring signals generated by the device under test according to the plurality of testing signals and generating a plurality of measuring results according to the predetermined manner. The determining module is coupled to the signal measuring module for determining a testing result for the device under test according to the plurality of measuring results.

摘要翻译： 公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括功能发生器，信号测量模块和确定模块。 功能发生器耦合到被测设备，以根据预定的方式提供多个测试信号。 信号测量模块耦合到被测设备和功能模块，用于根据多个测试信号测量被测器件产生的多个测量信号，并根据预定方式产生多个测量结果。 确定模块耦合到信号测量模块，用于根据多个测量结果确定被测设备的测试结果。

公开(公告)号：US20090015288A1

公开(公告)日：2009-01-15

申请号：US11898317

申请日：2007-09-11

申请人： Cheng-Yung Teng ,  Hung-Wei Chen

发明人： Cheng-Yung Teng ,  Hung-Wei Chen

IPC分类号： G01R31/00 ,  G09G3/36

CPC分类号： G01R31/31932 ,  G01R31/31924

摘要： A circuit testing apparatus for testing a device under test is disclosed. The circuit testing apparatus includes a function generator, a signal measuring module and a determining module. The function generator is coupled to the device under test for providing a plurality of testing signals according to a predetermined manner. The signal measuring module is coupled to the device under test and the function module for measuring a plurality of measuring signals generated by the device under test according to the plurality of testing signals and generating a plurality of measuring results according to the predetermined manner. The determining module is coupled to the signal measuring module for determining a testing result for the device under test according to the plurality of measuring results.

摘要翻译： 公开了一种用于测试被测设备的电路测试装置。 电路测试装置包括功能发生器，信号测量模块和确定模块。 功能发生器耦合到被测设备，以根据预定的方式提供多个测试信号。 信号测量模块耦合到被测设备和功能模块，用于根据多个测试信号测量被测器件产生的多个测量信号，并根据预定方式产生多个测量结果。 确定模块耦合到信号测量模块，用于根据多个测量结果确定被测设备的测试结果。

公开(公告)号：US20100090256A1

公开(公告)日：2010-04-15

申请号：US12249152

申请日：2008-10-10

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7843 ,  H01L29/7881

摘要： A semiconductor structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zones to yield stress different in level; and a barrier plug separating the two device zones from each other. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and a relatively lower reading voltage is needed to obtain initially required reading current. As a result, the probability of stress-induced leakage current (SILC) is reduced and the semiconductor memory structure may have enhanced data retention ability.

摘要翻译： 具有应力区域的半导体结构包括限定第一和第二器件区的衬底; 形成在所述第一和第二装置区域中的每一个中的第一和第二应力区域，以产生不同水平的应力; 以及将两个装置区彼此分开的阻挡塞。 由于在应力区产生的应力，载流子迁移率增加，因此可以获得增加的读取电流，并且需要相对较低的读取电压来获得最初需要的读取电流。 结果，应力诱发漏电流（SILC）的概率降低，并且半导体存储器结构可能具有增强的数据保留能力。

公开(公告)号：US20090140351A1

公开(公告)日：2009-06-04

申请号：US11948823

申请日：2007-11-30

申请人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

公开(公告)号：US07538351B2

公开(公告)日：2009-05-26

申请号：US11089405

申请日：2005-03-23

申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

公开(公告)号：US20090117695A1

公开(公告)日：2009-05-07

申请号：US12260674

申请日：2008-10-29

申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。